03/19-review(MIPS) Use general purpose registers with a load-store architecture: YES Provide at least 16 general purpose registers plus separate floating- point registers: 31 GPR& 32 FPR Support basic addressing modes: displacement (with an address offset size of 12 to 16 bits), immediate(size 8 to 16 bits), and register deferred; YES: 16 bits for immediate, displacement (disp=0=> register deferred All addressing modes apply to all data transfer instructions YES Use fixed instruction encoding if interested in performance and use variable instruction encoding if interested in code size Fixed Support these data sizes and types: 8-bit, 16-bit, 32-bit integers and 32-bit and 64-bit IEEE 754 floating point numbers: YES Support these simple instructions, since they will dominate the num ber of instructions executed load store add subtract. move register-register, and, shift, com pare equal, compare not equal branch with a PC-relative address at least 8-bits long), jump, call, and return: YES 16b Avim fpr a minimalist instryg19t学E Chapter 2.92021/2/11 中国科学技术大学 Chapter2.9 03/19-review (MIPS) • Use general purpose registers with a load-store architecture: YES • Provide at least 16 general purpose registers plus separate floating￾point registers: 31 GPR & 32 FPR • Support basic addressing modes: displacement (with an address offset size of 12 to 16 bits), immediate (size 8 to 16 bits), and register deferred; : YES: 16 bits for immediate, displacement (disp=0 => register deferred) • All addressing modes apply to all data transfer instructions : YES • Use fixed instruction encoding if interested in performance and use variable instruction encoding if interested in code size : Fixed • Support these data sizes and types: 8-bit, 16-bit, 32-bit integers and 32-bit and 64-bit IEEE 754 floating point numbers: YES • Support these simple instructions, since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and, shift, compare equal, compare not equal, branch (with a PC-relative address at least 8-bits long), jump, call, and return: YES, 16b • Aim for a minimalist instruction set: YES