Definition of Package Pinouts Control Signals (All control signals level actuated) resistor for the amp which is used to CS: Chip Select(active low). The CS in combination provide an output the DAC. This on-chip with ILE will enable WR1 resistor should used(not an external ILE: Input Latch Enable(active high). The ILE in com- resistor)since it le resistors which are bination with cs enables wr used in the on-chip R-2R ladder and tracks these WR,: Write 1. The active low WR, is used to load the resistors over temperature digital input data bits(DI) into the input latch. The VREF: Reference Voltage Input. This input connects an data in the input latch is latched when WR, is high extemal precision voltage source to the internal To update the input latch-CS and WR, must be low R-2R ladder VREF can be selected over the range while ILE is high. of +10 to-10V. This is also the analog voltage input WR2 Write 2(active low). This signal, in combination with for a 4-quadrant multiplying DAC application. XFER. causes the 8-bit data which is available in the Vcc: Digital Supply Voltage. This is the power supply input latch to transfer to the DAC register pin for the part. Vcc can be from +5 to +15voc Operation is optimum for +15Voc XFER: Transfer control signal (active low). The XFER will GND 10 voltage must be at the same ground Other Pin Functions of potential 10)will result in a linearity change of DIo DI7: Digital Inputs. DIo is the least significant bit(LSB) and DI, is the most significant bit(MSB) lOuT1: DAC Current Output 1. lOuT1 is a maximum for a Vos pin 10 digital code of all 1,s in the DAC register, and is zero for all Os in DAC register. lOUT?: DAC Current Output 2. louT? For example, if VReF 10V and pin 10 n OuT1, or louTH constant (I full scale for a lOUT1 and lOuTz the linearity change will be 0.03%. fixed reference voltage) Pin 3 can be offset t 100mv with no linearity change, but the Rt: Feedback Resistor. The feedback resistor is ogic input threshold will shift vided on the Ic chip for use as the shunt feed Linearity Error 坠 LSB ERRDR 1 LSB ERROR EAL RESPONSE a) End point test afterzero and fs b) Best straight line c)shifting fs adj. to pas best straight line test Definition of terms Resolution: Resolution is directly related to the number of after a single full scale adjust. (One adjustment vs. multiple switches or bits within the DAC. For example, the DAC0830 iterations of the adjustment. ) The"end point test"uses a has 2 or 256 steps and therefore has 8-bit resolution standard zero and F.s. adjustment procedure and is a much Linearity Error: Linearity Error is the maximum deviation more stringent test for DAC linearity. from a straight line passing through the endpoints of the Power Supply Sensitivity: Power supply sensitivity is a DAC transfer characteristic. It is measured after adjusting for measure of the effect of power supply changes on the DAC zero and full-scale. Linearity error is a parameter intrinsic to full-scale output the device and cannot be externally adjusted Settling Time: Settling time is the time required from a code National's linearity " end point test(a) and the "best straight transition until the daC output reaches within tyLSB of the line test(b, c)used by other suppliers are illustrated above final output value. Full-scale settling time requires a zero to The end point test" greatly simplifies the adjustment proce- full-scale or full-scale to zero output change dure by eliminating the need for multiple iterations of check Full Scale Error: Full scale error is a measure of the output g the linearity and then adjusting full scale until the linearity error between an ideal DAC and the actual device output. is met. The"end point test" guarantees that linearity is met ww.national. comDefinition of Package Pinouts Control Signals (All control signals level actuated) CS: Chip Select (active low). The CS in combination with ILE will enable WR1. ILE: Input Latch Enable (active high). The ILE in com￾bination with CS enables WR1. WR1: Write 1. The active low WR1 is used to load the digital input data bits (DI) into the input latch. The data in the input latch is latched when WR1 is high. To update the input latch–CS and WR1 must be low while ILE is high. WR2: Write 2 (active low). This signal, in combination with XFER, causes the 8-bit data which is available in the input latch to transfer to the DAC register. XFER: Transfer control signal (active low). The XFER will enable WR2. Other Pin Functions DI0-DI7: Digital Inputs. DI0 is the least significant bit (LSB) and DI7 is the most significant bit (MSB). IOUT1: DAC Current Output 1. IOUT1 is a maximum for a digital code of all 1’s in the DAC register, and is zero for all 0’s in DAC register. IOUT2: DAC Current Output 2. IOUT2 is a constant minus IOUT1 , or IOUT1 + IOUT2 = constant (I full scale for a fixed reference voltage). Rfb: Feedback Resistor. The feedback resistor is pro￾vided on the IC chip for use as the shunt feedback resistor for the external op amp which is used to provide an output voltage for the DAC. This on-chip resistor should always be used (not an external resistor) since it matches the resistors which are used in the on-chip R-2R ladder and tracks these resistors over temperature. VREF: Reference Voltage Input. This input connects an external precision voltage source to the internal R-2R ladder. VREF can be selected over the range of +10 to −10V. This is also the analog voltage input for a 4-quadrant multiplying DAC application. VCC: Digital Supply Voltage. This is the power supply pin for the part. VCC can be from +5 to +15VDC. Operation is optimum for +15VDC GND: The pin 10 voltage must be at the same ground potential as IOUT1 and IOUT2 for current switching applications. Any difference of potential (VOS pin 10) will result in a linearity change of For example, if VREF = 10V and pin 10 is 9mV offset from IOUT1 and IOUT2 the linearity change will be 0.03%. Pin 3 can be offset ±100mV with no linearity change, but the logic input threshold will shift. Linearity Error 00560823 a) End point test afterzero and fs adj. 00560824 b) Best straight line 00560825 c) Shifting fs adj. to pass best straight line test Definition of Terms Resolution: Resolution is directly related to the number of switches or bits within the DAC. For example, the DAC0830 has 28 or 256 steps and therefore has 8-bit resolution. Linearity Error: Linearity Error is the maximum deviation from a straight line passing through the endpoints of the DAC transfer characteristic. It is measured after adjusting for zero and full-scale. Linearity error is a parameter intrinsic to the device and cannot be externally adjusted. National’s linearity “end point test” (a) and the “best straight line” test (b,c) used by other suppliers are illustrated above. The “end point test’’ greatly simplifies the adjustment proce￾dure by eliminating the need for multiple iterations of check￾ing the linearity and then adjusting full scale until the linearity is met. The “end point test’’ guarantees that linearity is met after a single full scale adjust. (One adjustment vs. multiple iterations of the adjustment.) The “end point test’’ uses a standard zero and F.S. adjustment procedure and is a much more stringent test for DAC linearity. Power Supply Sensitivity: Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output. Settling Time: Settling time is the time required from a code transition until the DAC output reaches within ±1⁄2LSB of the final output value. Full-scale settling time requires a zero to full-scale or full-scale to zero output change. Full Scale Error: Full scale error is a measure of the output error between an ideal DAC and the actual device output. DAC0830/DAC0832 7 www.national.com