第十章.设计练习进阶 endmodule 测试模块源代码: compare lop.V timescale Ins/100ps include ./blockingv include ./non blockingv module compare Top wIre [3:0]bl,cl,b2,c2; reg initial cIk =0 forever #50 clk = clk nitia begin Display 4’h7 Display( #100 4 hf Display c Display ) 100 Display non blocking non blocking(clk, a, b2, c2) blocking(clk, a, bl, c1) endmodule 272第十章．设计练习进阶 endmodule 测试模块源代码： //------------- compareTop.v ----------------------------- `timescale 1ns/100ps `include "./blocking.v" `include "./non_blocking.v" module compareTop; wire [3:0] b1,c1,b2,c2; reg [3:0] a; reg clk; initial begin clk = 0; forever #50 clk = ~clk; end initial begin a = 4'h3; $display("____________________________"); # 100 a = 4'h7; $display("____________________________"); # 100 a = 4'hf; $display("____________________________"); # 100 a = 4'ha; $display("____________________________"); # 100 a = 4'h2; $display("____________________________"); # 100 $display("____________________________"); $stop; end non_blocking non_blocking(clk,a,b2,c2); blocking blocking(clk,a,b1,c1); endmodule 272