Feasibility constraints /96 Processor space vector and projection vector must be orthogonal to each other. p d=0 If node A and B differ by d,they must be executed by the same processor. If A and B are mapped to the same processor,then they cannot be executed at the same time,i.e. sTd≠0 Edge mapping:If an edge e exists in the space representation or DG,then an edge pe is introduced in the systolic array with se delays. 2021年2月 82021年2月 8 Feasibility constraints  Processor space vector and projection vector must be orthogonal to each other. p Td=0  If node A and B differ by d, they must be executed by the same processor.  If A and B are mapped to the same processor, then they cannot be executed at the same time, i.e. s Td0  Edge mapping: If an edge e exists in the space representation or DG, then an edge pTe is introduced in the systolic array with sTe delays