CONTENTS 8.6 Multicast Copy Networks 303 8.6.1 Broadcast Banyan Network /304 8.6.2 Encoding Process /308 8.6.3 Concentration /309 8.6.4 Decoding Process /310 8.6.5 Overflow and Call Splitting /310 8.6.6 Overflow and Input Fairness 311 9 KNOCKOUT-BASED SWITCHES 316 9.1 Single-Stage Knockout Switch /317 9.1.1 Basic Architecture /317 9.1.2 Knockout Concentration Principle /318 9.1.3 Construction of the Concentrator /320 9.2 Channel Grouping Principle /323 9.2.1 Maximum Throughput /324 9.2.2 Generalized Knockout Principle 325 9.3 Two-Stage Multicast Output-Buffered ATM Switch(MOBAS)/327 9.3.1 Two-Stage Configuration /327 9.3.2 Multicast Grouping Network (MGN)/330 9.4 Appendix /333 10 THE ABACUS SWITCH 336 10.1 Basic Architecture /337 10.2 Multicast Contention Resolution Algorithm /340 10.3 Implementation of Input Port Controller /342 10.4 Performance /344 10.4.1 Maximum Throughput /344 10.4.2 Average Delay /347 10.4.3 Cell Loss Probability 349 10.5 ATM Routing and Concentration (ARC)Chip 351 10.6 Enhanced Abacus Switch 354 10.6.1 Memoryless Multi-Stage Concentration Network /354 10.6.2 Buffered Multi-Stage Concentration Network 357 10.6.3 Resequencing Cells /359 10.6.4 Complexity Comparison 361 10.7 Abacus Switch for Packet Switching /362 10.7.1 Packet Interleaving 362 10.7.2 Cell Interleaving 364 11 CROSSPOINT BUFFERED SWITCHES 367 11.1 Combined Input and Crosspoint Buffered Switches /368Book1099 — “ftoc” — 2007/2/16 — 21:26 — page x — #6 x CONTENTS 8.6 Multicast Copy Networks / 303 8.6.1 Broadcast Banyan Network / 304 8.6.2 Encoding Process / 308 8.6.3 Concentration / 309 8.6.4 Decoding Process / 310 8.6.5 Overflow and Call Splitting / 310 8.6.6 Overflow and Input Fairness / 311 9 KNOCKOUT-BASED SWITCHES 316 9.1 Single-Stage Knockout Switch / 317 9.1.1 Basic Architecture / 317 9.1.2 Knockout Concentration Principle / 318 9.1.3 Construction of the Concentrator / 320 9.2 Channel Grouping Principle / 323 9.2.1 Maximum Throughput / 324 9.2.2 Generalized Knockout Principle / 325 9.3 Two-Stage Multicast Output-Buffered ATM Switch (MOBAS) / 327 9.3.1 Two-Stage Configuration / 327 9.3.2 Multicast Grouping Network (MGN) / 330 9.4 Appendix / 333 10 THE ABACUS SWITCH 336 10.1 Basic Architecture / 337 10.2 Multicast Contention Resolution Algorithm / 340 10.3 Implementation of Input Port Controller / 342 10.4 Performance / 344 10.4.1 Maximum Throughput / 344 10.4.2 Average Delay / 347 10.4.3 Cell Loss Probability / 349 10.5 ATM Routing and Concentration (ARC) Chip / 351 10.6 Enhanced Abacus Switch / 354 10.6.1 Memoryless Multi-Stage Concentration Network / 354 10.6.2 Buffered Multi-Stage Concentration Network / 357 10.6.3 Resequencing Cells / 359 10.6.4 Complexity Comparison / 361 10.7 Abacus Switch for Packet Switching / 362 10.7.1 Packet Interleaving / 362 10.7.2 Cell Interleaving / 364 11 CROSSPOINT BUFFERED SWITCHES 367 11.1 Combined Input and Crosspoint Buffered Switches / 368