B]: signal countl, count2: integer range 0 to 255: =0; signal clk: std_logic:=0, signal a, b integer: =165 signal data_bus: std_logic_vector(7 downto O); 信号赋值语句 目标信号<=表达式; 例:设计一个与非门电路 architecture one of nand 2is architecture one ofnand 2is signal ab: std_logic_vector(1 downto O); begin bes orocess(a 1S ab<=a& b: variable comb: std logic_vector(1 downto O); process(ab)is comb: =a b b egn begin case ab is case comb 1S when“00″=>c<= when“00”=>c<=‘1 when 111 when“01”=>c<=‘1 when“10 when >c<= when“11"=>c<="0 when11″=>c<=“0 when others =>null when others=>null; end case: end case en p rocess end process end one end one例：signal count1, count2: integer range 0 to 255 :=0; signal clk: std_logic :=‘0’; signal a, b: integer :=16; signal data_bus: std_logic_vector(7 downto 0); 信号赋值语句： 目标信号 <= 表达式； 例：设计一个与非门电路 architecture one of nand_2 is signal ab: std_logic_vector (1 downto 0); begin ab<=a & b; process(ab) is begin case ab is when “00” => c<=‘1’ ; when “01” => c<=‘1’ ; when “10” => c<=‘1’ ; when “11” => c<=‘0’ ; when others =>null; end case; end process; end one; architecture one of nand_2 is begin process(a，b) is variable comb: std_logic_vector (1 downto 0); comb:=a & b; begin case comb is when “00” => c<=‘1’ ; when “01” => c<=‘1’ ; when “10” => c<=‘1’ ; when “11” => c<=‘0’ ; when others =>null; end case; end process; end one;