Overview Make the pipelined processor work! Data Hazards a Instruction having register R as source follows shortly after instruction having register R as destination a Common condition, don't want to slow down pipeline Control Hazards a Mispredict conditional branch o Our design predicts all branches as being taken o Naive pipeline executes two extra instructions a Getting return address for ret instruction O PIPE-executes three extra instructions Making Sure It Really Works a What if multiple special cases happen simultaneously? Processor– 2 – Processor Overview Make the pipelined processor work! Data Hazards ◼ Instruction having register R as source follows shortly after instruction having register R as destination ◼ Common condition, don’t want to slow down pipeline Control Hazards ◼ Mispredict conditional branch ⚫ Our design predicts all branches as being taken ⚫ Naïve pipeline executes two extra instructions ◼ Getting return address for ret instruction ⚫ PIPE- executes three extra instructions Making Sure It Really Works ◼ What if multiple special cases happen simultaneously?