architecture one of rom is type memory is array(o to 15)of std_logic_vector(7 downto O) signal data1: memory:=(“10101001”,“11 11101001 11011100,“10111001”,“1100010,“11000101”, “00110100·1 00000100 1101100”,410001010”,“11001111 11000001 10011111 10100101” 0101110); signal addr1: integer range 0 to 15; addr1<=conv_integer(addr) process(en, addr1, addr, data1) then data<=datal(addr1) e data<=“ ZZZZZZZZ; nd if process d onearchitecture one of rom is type memory is array(0 to 15) of std_logic_vector(7 downto 0); signal data1:memory:=(“10101001”, “11111101”, “11101001”, “11011100”, “10111001”, “11000010”, “11000101”, “00000100”, “11101100”, “10001010”, “11001111”, “00110100”, “11000001”, “10011111”, “10100101”, “01011100”); signal addr1: integer range 0 to 15; begin addr1<=conv_integer(addr); process (en, addr1, addr, data1) begin if en=‘1’ then data<=data1(addr1); else data<=“ZZZZZZZZ”; end if; end process; end one;