use ieee std_logic_1164.all; use ieee std _logic_unsigned.all; entity mchange 1 port(clk, clr, ld:in std logic; m: in integer range0 to 99 g: bufferinteger range0 to 99) end mchange_1 architecture one of mchange_1 is signalmd: integer; egin process( clr, clk m) b d<=m-1; if cIr= 1 then g<=0; elsif clk event and clk=1 then fld=‘1’ then q<=m elsif q=md then q<=0; seq<=q+1; d if en end proces end one:library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mchange_1 is port(clk, clr, ld:in std_logic; m: in integer range 0 to 99; q: buffer integer range 0 to 99); end mchange_1; architecture one of mchange_1 is signal md: integer; begin process(clr,clk,m) begin md<=m-1; if clr=‘1’ then q<=0; elsif clk’event and clk=‘1’ then if ld=‘1’ then q<=m; elsif q=md then q<=0; else q<=q+1; end if; end if; end process; end one;