interrupts(中断) CPU Interrupt request line triggered by l/o device (cPU的中断需要有WO设备的触发) Interrupt handler receives interrupts (中断处理例程接收中断) Maskable to ignore or delay some interrupts (通过屏蔽来忽略或者延迟某些中断) o Interrupt vector to dispatch interrupt to correct handler (中断向量给中断分配正确的中断处理例程) Based on priority(以优先级为基础) Some unmaskable(某些中断不可屏蔽) Interrupt mechanism also used for exceptions (中断机制也用在异常) Applied Operating System Concepts 12.4 Silberschatz, Galvin, and Gagne @199912.4 Silberschatz, Galvin, and Gagne ©1999 Applied Operating System Concepts Interrupts（中断） • CPU Interrupt request line triggered by I/O device （CPU的中断需要有I/O设备的触发） • Interrupt handler receives interrupts （中断处理例程接收中断） • Maskable to ignore or delay some interrupts （通过屏蔽来忽略或者延迟某些中断） • Interrupt vector to dispatch interrupt to correct handler （中断向量给中断分配正确的中断处理例程） – Based on priority（以优先级为基础） – Some unmaskable（某些中断不可屏蔽） • Interrupt mechanism also used for exceptions （中断机制也用在异常）