Bank Cycle no. 5 0 144 2 busy 15 busy b 160 busy busy busy busy l68 5 busy busy busy busy busy 176 6 busy busy busy busy busy 184 192 busy b busy busy 8 busy 200 busy busy busy busy 9 busy busy 208 busybusy busy 10 busy busy busy 216 busy busy 11 busy busy busy b USV 224 busy 12 busy busybusybusybusy 232 13 busy b busy 240 14 busy busy busy busy 248 15 256 busy busy busy busy busy 16 busy 264 busy b busy Figure F7 Memory addresses (in bytes) by bank number and time slot at which access begins. Each memory bank latches the element address at the start of an access and is then busy for 6 clock cycles before returning a value to the CPU. Note that the CPU cannot keep all eight banks busy all the time because it is limited to supplying one new address and receiving one data item each cycle 1/272021 中国科学技术大学1/27/2021 中国科学技术大学 9