采用进程语句结构 libraryieee; 变量 use ieee std_logic_1164. all entity nand 3is port(a, b, c: in std_logic; y: out std_logic) end nand 3 architecture one of nand 3is process( a, b, c)is variable abc: std_logicvector( 2 do wnto O De abc =a &b& c case abc is when“000”=>y<=1 when“001″=>y< y When“010”=>y<=‘1’; when“011=>y<=1′; when“100 >y< when“101”=>y<=(1’; when“110″=>y<= when“1111y<=“0; when others=>null: end case, end process; end one?采用进程语句结构 ——变量 library ieee; use ieee.std_logic_1164.all; entity nand_3 is port(a,b,c:in std_logic; y: out std_logic); end nand_3; architecture one of nand_3 is begin process(a,b,c) is variable abc:std_logic_vector (2 downto 0); begin abc :=a & b & c; case abc is when “000” => y<=‘1’; when “001” => y<=‘1’; when “010” => y<=‘1’; when “011” => y<=‘1’; when “100” => y<=‘1’; when “101” => y<=‘1’; when “110” => y<=‘1’; when “111” => y<=‘0’; when others =>null; end case; end process; end one;