Addressing caches Figure 6.25 P488 Address a t bits s bits b bits ][tag[011…B-1 set 0: 01 <tag> <set index> <block offset> √][tag[o1…l-1 set 1: √囫g[01…-1 The word at address a is in the cache if the tag bits in one of the <valid> lines in [tag[01…1 set <set indexs match <tag. set s-1 vtag 01.B-The word contents begin at offset <block offset bytes from the beginning of the block9 Addressing caches Figure 6.25 P488 t bits s bits b bits m-1 0 <tag> <set index> <block offset> Address A: 0 1 • • • B–1 0 1 • • • B–1 v v tag tag set 0: • • • 0 1 • • • B–1 0 1 • • • B–1 v v tag tag set 1: • • • 0 1 • • • B–1 0 1 • • • B–1 v v tag tag set S-1: • • • • • • The word at address A is in the cache if the tag bits in one of the <valid> lines in set <set index> match <tag>. The word contents begin at offset <block offset> bytes from the beginning of the block