library ieee use ieee std_logic_1164. all; entity nand_3is port(a, b, c: in std_logic, y: out std_logic end nand 3 architecture one of nand 3 is b egin y<=not(a and b and c; end one;library ieee; use ieee.std_logic_1164.all; entity nand_3 is port(a,b,c:in std_logic; y: out std_logic); end nand_3; architecture one of nand_3 is begin y<=not (a and b and c); end one;