图5-598三态收发器74x245 (a)逻辑图(b)传统逻辑符号 例:74245双向总线缓冲器 use ieee std logic 1164. all entity k74245 is port(a, b: inout std logic vector(7 downto O); dir, g: in std logic); end K74245 architecture dfl of k74245 b<=a when(g=0)and(dir=0)else"ZZZZZZZZ a<=b when(g=0)and(dir='1")else(others=>Z) 注意:双向总线在功能仿真时的输入设置 a和b的输入不要同时存在;例： 74245 双向总线缓冲器 library ieee; use ieee.std_logic_1164.all; entity k74245 is port(a,b:inout std_logic_vector(7 downto 0); dir,g:in std_logic); end k74245; architecture dfl of k74245 is begin b<=a when (g = '0') and (dir = '0') else "ZZZZZZZZ"; a<=b when (g = '0') and (dir = '1') else (others=>'Z'); end dfl; 注意：双向总线在功能仿真时的输入设置 a 和 b 的输入不要同时存在；