vector(3 downto 0); y: out std logic vector( I downto 0)); end moore2. architecture beh of moore2 signal st: std logic vector(2 downto 0) constant sO: std logic vector(2 downto 0): =000 constant sl: std logic vector(2 downto 0): =010 constant s2: std logic vector(2 downto 0): =01 constant s3: std logic vector(2 downto 0): =110 constant s4: std logic vector(2 downto 0): ="lll process(clk, rst) if rst='I' then st<=s0 elsif clk'event and clka'l' then when s0=> if id=x"3"then st<=sl: else st<=s0: end if when sl=>st<=s2 when s2=> if id=x" 7"then st<=s3: else st<=s2: end if when s3=> if id=x"7"then st<=s0 elsif id=x 9"then st<=s4 else st<=s3 when s4=> if id=x"b"then st<=s0 else st<=s4 end if when others=>st<=s0 end case nd if y<=st(I downto 0)entity moore2 is port(clk,rst: in std_logic; id: in std_logic_vector(3 downto 0); y: out std_logic_vector(1 downto 0)); end moore2; architecture beh of moore2 is signal st: std_logic_vector(2 downto 0); constant s0:std_logic_vector(2 downto 0):="000"; constant s1:std_logic_vector(2 downto 0):="010"; constant s2:std_logic_vector(2 downto 0):="011"; constant s3:std_logic_vector(2 downto 0):="110"; constant s4:std_logic_vector(2 downto 0):="111"; begin process(clk,rst) begin if rst='1' then st<=s0; elsif clk'event and clk='1' then case st is when s0=> if id=x"3" then st<=s1;else st<=s0;end if; when s1=> st<=s2; when s2=> if id=x"7" then st<=s3;else st<=s2;end if; when s3=> if id=x"7" then st<=s0; elsif id=x"9" then st<=s4;else st<=s3; end if; when s4=> if id=x"b" then st<=s0;else st<=s4;end if; when others=>st<=s0; end case; end if; end process; y<=st(1 downto 0); end beh;