DS12887 DSE The Daylight Savings Enable(DSE)bit is a read/write bit which enables two special updates when DSE is set to 1.On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM.On the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM.These special updates do not occur when the DSE bit is a 0.This bit is not affected by internal functions or RESET. REGISTER C MSB LSB BIT 7 BIT6 BIT 5 BIT4 BIT3 BIT2 BIT 1 BIT0 IRQF PF UF 0 0 0 0 IRQF The Interrupt Request Flag(IRQF)bit is set to a 1 when one or more of the following are true: PF=PIE=1 AF=AIE=1 UF=UIE=1 That is,IRQF=PF·PIE+AF·AIE+UF·UE. Any time the IRQF bit is a 1,the IRQ pin is driven low.All flag bits are cleared after Register C is read by the program or when the RESET pin is low PF The Periodic Interrupt Flag(PF)is a read-only bit which is set to a 1 when an edge is detected on the selected tap of the divider chain.The RS3 through RSO bits establish the periodic rate.PF is set to a I independent of the state of the PIE bit.When both PF and PIE are Is,the IRQ signal is active and will set the IRQF bit.The PF bit is cleared by a RESET or a software read of Register C. AF A 1 in the Alarm Interrupt Flag(AF)bit indicates that the current time has matched the alarm time.If the AIE bit is also a 1,the IRQ pin will go low and a 1 will appear in the IRQF bit.A RESET or a read of Register Cwill. UF The Update Ended Interrupt Flag (UF)bit is set after each update cycle.When the UIE bit is set to 1,the one in UF causes the IRQF bit to be a 1,which will assert the IRQ pin.UF is cleared by reading Register Cor a RESET BIT 0 THROUGH BIT 3 These are unused bits of the status Register C.These bits always read 0 and cannot be written REGISTER D MSR LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT3 BIT2 BIT 1 VRT 0 0 0 11of19 DS12887 11 of 19 DSE The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These special updates do not occur when the DSE bit is a 0. This bit is not affected by internal functions or RESET . REGISTER C MSB LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IRQF PF AF UF 0 0 0 0 IRQF The Interrupt Request Flag (IRQF) bit is set to a 1 when one or more of the following are true: PF = PIE = 1 AF = AIE = 1 UF = UIE = 1 That is, IRQF = PF · PIE + AF · AIE + UF · UIE. Any time the IRQF bit is a 1, the IRQ pin is driven low. All flag bits are cleared after Register C is read by the program or when the RESET pin is low. PF The Periodic Interrupt Flag (PF) is a read–only bit which is set to a 1 when an edge is detected on the selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1 independent of the state of the PIE bit. When both PF and PIE are 1s, the IRQ signal is active and will set the IRQF bit. The PF bit is cleared by a RESET or a software read of Register C. AF A 1 in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm time. If the AIE bit is also a 1, the IRQ pin will go low and a 1 will appear in the IRQF bit. A RESET or a read of Register C will clear AF. UF The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to 1, the one in UF causes the IRQF bit to be a 1, which will assert the IRQ pin. UF is cleared by reading Register C or a RESET . BIT 0 THROUGH BIT 3 These are unused bits of the status Register C. These bits always read 0 and cannot be written. REGISTER D MSB LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VRT 0 0 0 0 0 0 0