use ieeestd logic 1164. all entity inv 16 is port (x: in std logic vector(15 downto 0); nd invi y:out std_logic_vector(15 downto 0)); architecture s of inv 16 is component bu generic(width: positive: =4) ort (x: in std logic vector(width-l downto 0); y:out std logic vector (width-1 downto 0)); end component ul: busin generic map(16) port map(x, y); 元件语句的简化使用一宏调用 只要进行相应的资源说明,可以不在结构体中进行元件说明; 例16位总线反相器的结构设计(work库的使用) library iee use ieee std logic 1164 all use work. all entity inv 16 is port(x: in std logic vector(15 downto 0) y: out std logic vector(15 downto 0)); end inv16. architecture s of inv 16 is ul: busin generic map(16) port map(x,y);use ieee.std_logic_1164.all; entity inv16 is port (x: in std_logic_vector (15 downto 0); y:out std_logic_vector (15 downto 0) ); end inv16; architecture s of inv16 is component businv is generic (width:positive:=4); port (x: in std_logic_vector (width-1 downto 0); y:out std_logic_vector (width-1 downto 0) ); end component; begin u1: businv generic map(16) port map (x,y); end s; 元件语句的简化使用—宏调用 只要进行相应的资源说明，可以不在结构体中进行元件说明； 例 16 位总线反相器的结构设计 （work 库的使用） library ieee; use ieee.std_logic_1164.all; use work.all; entity inv16 is port (x: in std_logic_vector (15 downto 0); y:out std_logic_vector (15 downto 0) ); end inv16; architecture s of inv16 is begin u1: businv generic map(16) port map (x,y);