libraryieee, useieee.std _logic_1164. all; useieee. std logic unsigned. all entity addis port(a, b, ci:in std logic, S,co: out std _ logic) end add1 architecture one of add1 is signal temp: std _logic_vector(1 downto 0 begin temp<=("0′&a)+b+c; s<=temp(o) co<=temp(1) end onelibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity add1 is port(a,b, ci:in std_logic; s,co: outstd_logic); end add1; architecture one of add1 is signal temp: std_logic_vector(1 downto 0); begin temp<=(‘0’&a )+b+ci; s<=temp(0); co<=temp(1); end one;