Altera provide example File Edit Book 旦 ptions Help Implementing RAM& ROM VHDL on on Synchronous or asynchronous ROM csdpram Cycle-shared dual-port RAM Csiro Cycle-shared first-in first-out (FIFO)buffer In these functions, parameters are used to determine the input and out put data widths: th memory: whether data inputs, address/control inputs, and outputs are registered or unreg ontent file is to be included for a RAM block; and so on. You must declare parameter n ROM function by using Generic Map Aspects. The following example shows a 256 x 8 bi separate input and output ports 工工 BRARY ieee e.std_1口giC_1164.矗工 工 BRARY1pm USE work ram c tants,A工工 ENTITY ram256x8 IS PORT( data: IN STD LOGIC VECTOR (DATA WIDTH-1 DOWNTO 0) ddress: IN STI工 R (ADDR WIDTH-1 DOWNTO 0) we g: OUT STD LOGIC VECTOR (DA 工DT 1 DOWNTO 0)) END ra25638 ARCHI TECTURE example OF ram256x8 IS BEGIN inst 1: lpm ram da GENERIC MAP (lpm widthad - ADDR WIDTH PORt MaP (data = data, address = address, we =>we inclock = inclock. outclock = outclock, C=>g END exampleCopyright © 1997 Altera Corporation 2/22/2021 Altera provide example