第3卷第5期 智能系统学报 Vol 3 Na 5 2008年10月 CAA I Transactions on Intelligent Systems 0ct2008 基于动态可重构FPGA的自演化硬件概述 姚爱红张国印，关琳 哈尔滨工程大学计算机科学与技术学院，黑龙江哈尔滨150001) 摘要：演化硬件研究如何利用遗传算法进行硬件自动设计，或者设计随外界环境变化而自适应地改变自身结构的 硬件，在电子设计自动化、自主移动机器人控制器、无线传感器网络节点等领域都有潜在的应用价值.自演化硬件是 在硬件内部完成遗传操作和适应度计算，利用支持动态部分可重构的FPGA芯片上的微处理器核实现遗传算法，模 拟生物群体演化过程搜索可能的电路设计并配置片上的可重构逻辑，找到最优或较优的设计结果，从而实现自适应 硬件.当电路发生故障时，自演化硬件自动搜索新的配置，利用片上冗余资源取代故障区域，从而实现自修复硬件」 介绍了基于动态部分可重构FPGA的自演化硬件的基本思想、体系结构以及研究现状，总结并提出了亟待解决的关 键技术，指出高效的电路染色体编码表示与可重构逻辑配置位串之间的映射方式是当前研究的重点之一 关键词：演化硬件：动态可重构；染色体编码；FPGA 中图分类号：TP303文献标识码：A文章编号：1673-4785(2008)05043607 A survey of dynam ica lly and partally reconfigurable FPGA-ba sed self-evolva ble hardware YAO A i-hong,ZHANG Guo-yin,GAN L in (College of Computer Science and Technolgy,Harbin Engineering University,Harbin 150001,China) Abstract:The objective of evolvable hardware (EHW research is the devebpment of automated electronic-circuit design,or a system capable of adap tive alterations to the hardware of its structure EHW has a great variety of ap- plications in fields such as design automation,controllers for autonomous mobile robots,and wireless sensor net work nodes Self-evolutionary hardware completes genetic operations and the evaluation of fitness in an on-chip mi- croprocessor The on-chip m icropocessor core of the dynam ically and partially reconfigurable field-programmable gate array (FPGA)runs the genetic algorithm,smulates the evolving process to search for possible circuits,and then sets the on-chip reconfigurable logic so that it runs designs which are superior to the originalmanmade ones, or are optmal designs In this way adaptive hardware is possible When a circuit fails,the self-evolutionary hard- ware can automatically search for new configurations,using the abundant resources on the chip to replace the failed area,realizing the goal of self-repairing hardware In this paper,the ideas behind self-EHW research,the archi- tecture of self-EHW and the latest progress in the area are studied The prmary problems to be solved are then summarized Finally,future research directions are pointed out,such as ways o establish a highly efficient map- ping mode be ween chromosomal encoding of circuits and the configuration bit strings of reconfigurable logic Keywords:evolvable hardware;dynam ical reconfiguration;chromosome encoding FPGA 随半导体工艺水平的迅速提高，单个芯片所能距越来越大.演化硬件(evolvable hardware,EfW) 提供的晶体管数目达到十亿量级，基于电子设计自 利用硬件自身的快速并行计算能力在可能的设计空 动化(electronic design automation,EDA)软件工具 间进行搜索，从而实现硬件的自动设计，成为计算机 的传统设计方法的设计能力与芯片集成度之间的差 系统结构和电子设计自动化领域的研究热点之 一s].利用演化算法(evolutionary algrithm,EA)在 收稿日期：200706-19 通信作者：姚爱红.Email yaoaihong@hrbeu edu cn 传统设计空间内进行搜索，有可能找到比手工设计 1994-2009 China Academic Journal Electronic Publishing House.All rights reserved.http://www.cnki.net第 3卷第 5期 智 能 系 统 学 报 Vol. 3 №. 5 2008年 10月 CAA I Transactions on Intelligent System s Oct. 2008 基于动态可重构 FPGA的自演化硬件概述 姚爱红 ,张国印 ,关 琳 (哈尔滨工程大学 计算机科学与技术学院 ,黑龙江 哈尔滨 150001) 摘 要 :演化硬件研究如何利用遗传算法进行硬件自动设计 ,或者设计随外界环境变化而自适应地改变自身结构的 硬件 ,在电子设计自动化、自主移动机器人控制器、无线传感器网络节点等领域都有潜在的应用价值. 自演化硬件是 在硬件内部完成遗传操作和适应度计算 ,利用支持动态部分可重构的 FPGA芯片上的微处理器核实现遗传算法 ,模 拟生物群体演化过程搜索可能的电路设计并配置片上的可重构逻辑 ,找到最优或较优的设计结果 ,从而实现自适应 硬件. 当电路发生故障时 ,自演化硬件自动搜索新的配置 ,利用片上冗余资源取代故障区域 ,从而实现自修复硬件. 介绍了基于动态部分可重构 FPGA的自演化硬件的基本思想、体系结构以及研究现状 ,总结并提出了亟待解决的关 键技术 ,指出高效的电路染色体编码表示与可重构逻辑配置位串之间的映射方式是当前研究的重点之一. 关键词 :演化硬件 ;动态可重构 ;染色体编码 ; FPGA 中图分类号 : TP303 文献标识码 : A 文章编号 : 167324785 (2008) 0520436207 A survey of dynam ically and partially reconfigurable FPGA2based self2evolvable hardware YAO A i2hong, ZHANG Guo2yin, GUAN L in (College of Computer Science and Technology, Harbin Engineering University, Harbin 150001, China) Abstract: The objective of evolvable hardware (EHW ) research is the development of automated electronic2circuit design, or a system capable of adap tive alterations to the hardware of its structure. EHW has a great variety of ap2 p lications in fields such as design automation, controllers for autonomous mobile robots, and wireless sensor net2 work nodes. Self2evolutionary hardware comp letes genetic operations and the evaluation of fitness in an on2chip m i2 crop rocessor. The on2chip m icrop rocessor core of the dynam ically and partially reconfigurable field2p rogrammable gate array (FPGA) runs the genetic algorithm, simulates the evolving p rocess to search for possible circuits, and then sets the on2chip reconfigurable logic so that it runs designs which are superior to the original man2made ones, or are op timal designs. In this way adap tive hardware is possible. W hen a circuit fails, the self2evolutionary hard2 ware can automatically search for new configurations, using the abundant resources on the chip to rep lace the failed area, realizing the goal of self2repairing hardware. In this paper, the ideas behind self2EHW research, the archi2 tecture of self2EHW and the latest p rogress in the area are studied. The p rimary p roblem s to be solved are then summarized. Finally, future research directions are pointed out, such as ways to establish a highly efficient map2 p ing mode between chromosomal encoding of circuits and the configuration bit strings of reconfigurable logic. Keywords: evolvable hardware; dynam ical reconfiguration; chromosome encoding; FPGA 收稿日期 : 2007206219. 通信作者 :姚爱红. E2mail: yaoaihong@hrbeu. edu. cn 随半导体工艺水平的迅速提高 ,单个芯片所能 提供的晶体管数目达到十亿量级 ,基于电子设计自 动化 ( electronic design automation, EDA )软件工具 的传统设计方法的设计能力与芯片集成度之间的差 距越来越大. 演化硬件 ( evolvable hardware, EHW ) 利用硬件自身的快速并行计算能力在可能的设计空 间进行搜索 ,从而实现硬件的自动设计 ,成为计算机 系统结构和电子设计自动化领域的研究热点之 一 [ 123 ] . 利用演化算法 ( evolutionary algorithm, EA )在 传统设计空间内进行搜索 ,有可能找到比手工设计 © 1994-2009 China Academic Journal Electronic Publishing House. All rights reserved. http://www.cnki.net