《工程科学学报》录用稿，htps:/doi.org/10.13374/i,issn2095-9389.2021.10.08.003©北京科技大学2020 工程科学学报DO: 龙芯处理器服务器芯片组的适配与实现 郑臣明)，姚宣霞区，周芳)，郑雪峰)，杨晓君)，戴荣) 1)北京科技大学计算机与通信工程学院，北京1000832)海光倍息技术股份有限公司，北京1001933)中科曙光信息产业成都有限公司， 四川610213 ☒通信作者，E-mail:yaoxuanxia@ustb.edu.cn 摘要针对龙芯CPU无对应高性能服务器芯片组的现状，设计开发了一种为龙芯P火筛选芯片组的架构，并实现 了一种龙芯CPU和芯片组适配的方法。提出了采用现场可编程门阵列(FPGA)串联在龙芯CPU和即将适配的多组 芯片组之间的架构。借助于此架构，设计实现了在CPU和芯片组之间那些暂时不知何处理的物理信号线的连接方 法，设计了两者之间上下电时序配合的调试方法，设计实现了规避两者信号协仪鉴导的方法。借助这种架构和这些 方法能够实现同时筛选多款芯片组的目的，避免了以前需要设计多款主板进行适配的情况，节省了重复研发主板的 成本：找到了可以适配龙芯CPU的高性能服务器芯片组：其芯片组规格参数和性能高于目前龙芯CPU所用的芯片 组，开拓了其在服务器领域的应用。 关键词龙芯：芯片组：适配：服务器：现场可编程门阵列 分类号TP302.1 Adaption and implementation of server chipsets for loongson CPU ZHENG Chen-ming,YAO Xuan ZHOU Fang,ZHENG Xue-feng YANG Xiao-ju,DAI Rong 1)School of Computer Communication Eng niversity of Science&Technology Beijing,Beijing 100083,China 2) Haiguang Information Technology ng.100193.China 3) Dawning Information Industry uan,610213,China Corresponding author, ia@ustb.edu.cn ABSTRACT CPl is the core part among all of integrated circuits.Although some homemade CPUs of proprietary intellectual property rights are rapidly developed,there are few high performance chipsets,especially in server domain,to match them.Thus total systems designed by means of those CPUs and low performance chipsets don't release proper performance.Loongson CPU faces the same problem.In seek of better chipsets,a certain architecture and some methods are designed and implemented to adapt some different types of chipsets for it.In this architecture,the field programmable gate array(FPGA)is linked between CPU and these chipsets.FPGA is divided into three domains,which are HT(Hyper Transport) bus domain,processing domain for important but temporarily indeterminate signals,CPLD(Complex Programmable Logic Device)function domain.In these processes of adaption,HT bus signals,the temporarily indeterminate signals and power signals in both CPU and chipsets are respectively linked into three domains in FPGA and treated by programming FPGA to 收毫日期2021-10-08 签项自：国家重大科技专项“核心电子器件、高端通用芯片及基础软件产品”资助项目(2017ZX01028-102)工程科学学报 DOI: 龙芯处理器服务器芯片组的适配与实现1 郑臣明 1)，姚宣霞 1)，周 芳 1)，郑雪峰 1)，杨晓君 2)，戴荣 3) 1）北京科技大学计算机与通信工程学院，北京 100083 2）海光信息技术股份有限公司，北京 100193 3）中科曙光信息产业成都有限公司， 四川 610213  通信作者，E-mail: yaoxuanxia@ustb.edu.cn 摘 要 针对龙芯 CPU 无对应高性能服务器芯片组的现状，设计开发了一种为龙芯 CPU 筛选芯片组的架构，并实现 了一种龙芯 CPU 和芯片组适配的方法。提出了采用现场可编程门阵列（FPGA）串联在龙芯 CPU 和即将适配的多组 芯片组之间的架构。借助于此架构，设计实现了在 CPU 和芯片组之间那些暂时不知如何处理的物理信号线的连接方 法，设计了两者之间上下电时序配合的调试方法，设计实现了规避两者信号协议差异的方法。借助这种架构和这些 方法能够实现同时筛选多款芯片组的目的，避免了以前需要设计多款主板进行适配的情况，节省了重复研发主板的 成本；找到了可以适配龙芯 CPU 的高性能服务器芯片组；其芯片组规格参数和性能高于目前龙芯 CPU 所用的芯片 组，开拓了其在服务器领域的应用。 关键词 龙芯；芯片组；适配；服务器；现场可编程门阵列 分类号 TP302.1 Adaption and implementation of server chipsets for loongson CPU ZHENG Chen-ming 1) , YAO Xuan-xia 1) , ZHOU Fang1) , ZHENG Xue-feng1) , YANG Xiao-jun2) , DAI Rong3) 1) School of Computer & Communication Engineering, University of Science & Technology Beijing, Beijing 100083, China 2) Haiguang Information Technology Co., Ltd., Beijing, 100193, China 3) Dawning Information Industry Co., Ltd., Sichuan, 610213, China  Corresponding author, E-mail: yaoxuanxia@ustb.edu.cn ABSTRACT CPU is the core part among all of integrated circuits. Although some homemade CPUs of proprietary intellectual property rights are rapidly developed, there are few high performance chipsets, especially in server domain, to match them. Thus total systems designed by means of those CPUs and low performance chipsets don’t release proper performance. Loongson CPU faces the same problem. In seek of better chipsets, a certain architecture and some methods are designed and implemented to adapt some different types of chipsets for it. In this architecture, the field programmable gate array(FPGA) is linked between CPU and these chipsets. FPGA is divided into three domains, which are HT(Hyper Transport) bus domain, processing domain for important but temporarily indeterminate signals, CPLD(Complex Programmable Logic Device) function domain. In these processes of adaption, HT bus signals, the temporarily indeterminate signals and power signals in both CPU and chipsets are respectively linked into three domains in FPGA and treated by programming FPGA to 1收稿日期:2021-10-08 基金项目: 国家重大科技专项“核心电子器件、高端通用芯片及基础软件产品”资助项目(2017ZX01028-102) 《工程科学学报》录用稿，https://doi.org/10.13374/j.issn2095-9389.2021.10.08.003 ©北京科技大学 2020 录用稿件，非最终出版稿