04毫米波雷达实验平台架构 历安毛子代技大势 实验平台架构 Seral Flash interface Cortex R4F LNA ADC @200MH MCUimerface LNA ADC Digital 5m/2c Front-end ADC DCAN DMA CAN-FD NA ADC For debug Master sub-system (Customer programmed) T PA △中 Mailbox LVDS PA Ramp High-speed input for C674x DSP HIL hardware-in-loop veriscation @400/600MHz △中 Radio (BIST) GPADC L1D &ete组-l 33) L2(256kB) programmed) VMON Temp DMA CRC Radio processor sub-system DSP sub-system RF/Analog sub-system (TI programmed) ustorner prog￥nsd】 .Up to 512kB of Radar Data Memory can be swtched to the Master RAF program and data RAMs 厚德求真砺学笃行 3 XIDIAN UNIVERSITY 13 实验平台架构 04 毫米波雷达实验平台架构