4-bit synchronous counter More complicated than asynchronous design fromhttp://web.cs.munca/paul/cs3724/material/web/notes/img191.png F Clock VHDL 6. examples of FSM ver. 8a4-bit synchronous counter • More complicated than asynchronous design • from http://web.cs.mun.ca/~paul/cs3724/material/web/notes/img191.png VHDL 6. examples of FSM ver.8a 10