2器时 【例11-1】 library ieee use ieee std logic 1164.alli use ieee std logic unsigned alli entity cnt4 is port (d: in std logic vector (3 downto 0)i ld, ce, clk, rst in std logici g: out std logic vector (3 downto o))i end cnt4 archi tecture behave of cnt4 is signal count std logic vector (3 downto o)i begin process (clk, rst begin if rst=l then count <=(others =>0)i elsif rising edge(clk)then if ld =1 then count < elsif ce 'l then count < count l end ifi end if; end processi g < counti end behave康芯科技 【例11-1】 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt4 is port (d : in std_logic_vector (3 downto 0); ld, ce, clk, rst : in std_logic; q : out std_logic_vector (3 downto 0)); end cnt4; architecture behave of cnt4 is signal count : std_logic_vector (3 downto 0); begin process (clk, rst) begin if rst = '1' then count <= (others => '0'); elsif rising_edge(clk) then if ld = '1' then count <= d; elsif ce = '1' then count <= count + 1; end if; end if; end process; q <= count; end behave;