基本逻辑单元的设计 例:3输入端异或门y=a⊕bc 参见p417表546 architecture rtl of kxor 3 is signal yl: std logIc, begin <=a xor b xor c y<=yl after 3 ns when y1=else yI after 5 ns when y1=0 end rti基本逻辑单元的设计 例：3输入端异或门 参见 p.417 表5-46 architecture rtl of kxor3 is signal y1: std_logic; begin y1<= a xor b xor c ; y<= y1 after 3 ns when y1='1' else y1 after 5 ns when y1='0' ; end rtl; y = abc