3. Step coverage, and 4. Patterning Step coverage is controlled by the deposition method Patterning method is controlled by the chemistry of the material Dep method Etch method Al-Si-Cu Sputter RIE in CCl4 or wet etch* in acetic/nitric acid W CVD etch or CMP poly-SI CVD Nitric acid P late, sputter Damascene CMP *undesirable for very small features ll/703 3.155J6.l52J Cu by damas cene process Cu problem: difficult to etch, also it reacts with Si degrades the operation of the transistors Solution: Damascene process for deposition: does not require etching. Make trenches, deposit plating base, then fill with electrodeposition and polish surface. The vias can be made simultaneously in a dual damascene process. Al can also be deposited by a damascene process(sputter and reflow to fill trenches) use diffusion barriers to prevent diffusion, e.g. TIN(made by CVD) ll/703 3.155J6.l52J3. Step coverage, and 4. Patterning Step coverage is controlled by the deposition method; Patterning method is controlled by the chemistry of the material. Dep. method Etch method Al-Si-Cu Sputter RIE in CCl4 or wet etch* in acetic/nitric acid W CVD etch or CMP poly-Si CVD Nitric acid Cu P late , sputter Damascene, CMP *undesirable for very small features 11/17/03 3.155J/6.152J 13 Cu by damascene process Cu problem: difficult to etch; also it reacts with Si, degrades the operation of the transistors. Solution: Damascene process for deposition: does not require etching. Make trenches, deposit plating base, then fill with electrodeposition and polish surface. The vias can be made simultaneously in a dual￾damascene process. Al can also be deposited by a damascene process (sputter and reflow to fill trenches). polish Cu dielectric barrier use diffusion barriers to prevent diffusion, e.g.TiN (made by CVD). 11/17/03 3.155J/6.152J 14 7