METALLIZATION INTERCONNECTS Read: Plummer Chapter I 1; Campbell Chapter 15 Why do we need metallization?- To connect devices electrically to each other and to the outside world; power and data Local interconnect doped polySi, silicides Packaging Cu or Al(several mm per chip) Materials choices for interconnects, more complex multilayer interconnects ll/703 3.155J6.l52J Generic metallization layout ontact(local interconnect) ll/703 3.155J6.l52J
METALLIZATION, INTERCONNECTS Read: Plummer Chapter 11; Campbell Chapter 15 Why do we need metallization? - To connect devices electrically Local interconnects: • gate contacts: doped polySi, silicides Inter-level to each other and to the outside world; power and data. • plugs, vias, e.g. W Packaging • Longer range interconnects: Cu or Al (several mm per chip) Materials choices for interconnects, more complex multilayer interconnects. 11/17/03 3.155J/6.152J 1 Generic metallization layout gate contact (local interconnect) Plug, via metal lines (global interconnects) 11/17/03 3.155J/6.152J 2 1
Requirements for metallization: 1. Low electrical resistivity 2. Electrical contact with device(Ohmic or Schottky) methods(can it be etched?) 5. Thermal and mechanical stability 6. Reliability in service, e.g. electro-migration. Next week (beside metallization inter-metal dielectrics are equally important ll/703 3.155J6.l52J l. Resistivity, why low Crudely: I=I cm/ Fringe field factor TL-RC-1.8K. -_1I T2=36K Local interconnects L F r2=10-7sec Global interconnects A few m Chip area(mm-) ll/703 3.155J6.l52J
Requirements for metallization: 1. Low electrical resistivity 2. Electrical contact with device (Ohmic or Schottky) 3. Step coverage 4. Patterning methods (can it be etched?) 5. Thermal and mechanical stability 6. Reliability in service, e.g. electro-migration. Next week (beside metallization, inter-metal dielectrics are equally important …) 11/17/03 3.155J/6.152J 3 ox ≈ Fmin oxe0r ËHxox s WL ¯ Ë Fmin ¯ k 4 ox t L ª10-17 10-8 t L = RCª1.8k e0rL2 Á ˜ + H,Ls, xox t L ª 3.6k Á ˜ t gate ª10-11 min = 0.25 microns WSi2 W Al Cu for F Poly Si Local interconnects L Fmin sec Delay Global interconnects L A few mm t L ª10-9 sec time (sec) Inductive effects 2 -3 orders smaller; t ind = (LC) 10-12 1 10 100 Chip area (mm2 ) 11/17/03 3.155J/6.152J 4 Crudely: t = 1 cm/c = 10-8 sec but if e > e 0, t = 1 cm (eµ) > 10-8 sec Compared to gate times of order 10-11 sec L WL R = r C = koxe0 WH xox Fringe field factor Ê 1 1 HL + koxe0 L 1. Resistivity, why low? CI Cs R L H Ls W s ˆ 2 ˆ Ê L 2
1. Resistivity Properties of interconnect materiak resistivity Which material Melting point (C) is better for local and which for 40-70 28-35 15-20 polysilicon(heavily doped) Properties of commonly used interconnected materials in both Si and GaAs technologies Material Bulk Resistivity(uf2-cm Melting Point (C) LAu use for gaAs 2. Ohmic and Schottky junctie ons Even after selecting conductor material no guarantee it will make good electrical contact to Si, GaAs, etc Nature of contact depends on charge transfer at metal/semiconductor interface charging = band bending bending depends on work functions, m, and electron affinity, x Vacuum E Metal n-type semiconductor ll/703 3.155J6.l52J
3 11/17/03 3.155J/6.152J 5 1. Resistivity Which material is better for local and which for global interconnects? use for GaAs 11/17/03 3.155J/6.152J 6 2. Ohmic and Schottky junctions Even after selecting conductor material, no guarantee it will make good electrical contact to Si, GaAs, etc. Nature of contact depends on charge transfer at metal/semiconductor interface; charging => band bending & bending depends on work functions, fm , fs and electron affinity, c. Ef Energy Metal n-type semiconductor Vacuum fm c fs Ef Ec Ev
Background for Schottky barriers When a p-n junction is formed.. (depletion region) =>E field tha there is a net flow of camers halts flow of e's across interface. until energy difference is neutralized and What happens at semiconductor/metal interface ll/703 3.155J6.l52J Schottky barriers When a meta- type semiconductor junction is formed withφa>中… Vacuum Mobile es Heavily n here is a net flow of camers intill energy difference is neutralized and Fermi energies come to a common value depletion region(length governed by screening length) ll/703 3.155J6.l52J
Background for Schottky barriers When a p-n junction is formed... Mobile e’s p Mobile holes Immobile e’s n Immobile holes e - EF EF EF E Excess e’s h’s (depletion region) => E field that halts flow of e’s ... there is a net flow of carriers across interface… until energy difference is neutralized and Fermi energies come to a common value. What happens at semiconductor/metal interface… 11/17/03 3.155J/6.152J 7 fm fs Schottky barriers When a metal -n-type semiconductor junction is formed with > ... Vacuum Vacuum Mobile e’s Immobile holes e - ... there is a net flow of carriers across interface… fm fs n EF EF EF Mobile e’s n fm E Heavily doped EF Lightly doped until energy difference is neutralized and Fermi energies come to a common value. w depletion region (length governed by screening length) 11/17/03 3.155J/6.152J 8 4
Ideal Schottky junction: m>ps, n-type semiconducto here is a barrier B Vacuum preventing electrons from going E from metal to n-type semiconductor There is an internal field keeping EF carriers away from junction. This junction behaves like a diode f中n<中 there is no barrier for n-type ll/703 3.155J6.l52J
Ideal Schottky junction: > There is a barrier n-type semiconductor. fB M o b i l e e’s n fm E preventing electrons from going from metal to EF EF f , n-type semiconductor s There is an internal field keeping carriers away from junction. This junction behaves like a diode. Vacuum If < there is no barrier for n-type semiconductor (Ohmic). ln I fm V fB 11/17/03 3.155J/6.152J 9 fs fm 5
Metallic electrons can only go over barrier by thermionic emission tunnel or or can tunnel through hermio if it is narrow (highly doped If pm>p = Schottky contact with n-type semiconductor Ohmic with p-type If m< o Schottky contact with p-type semiconductor Ohmic with n-type ll/703 3.155J6.l521 should determine contact type but in practice surface contamination and traps nd usually have Schottky barrier To obtain Ohmic contact, make barrier very narrow very heavy doping (n*or p*- 1020 cm-3 adjacent to the metal Al is a p dopant 11/17/03 3.155J6.l52J
Metallic electrons can only go over barrier by thermionic emission, tunnel or or can tunnel through thermioic if it is narrow (highly doped). If fm s > f => Schottky contact with n-type semiconductor Ohmic with p-type If fm s Schottky contact with p-type semiconductor Ohmic with n-type 11/17/03 3.155J/6.152J 11 The metal work function should determine contact type, but in practice, surface contamination and traps pin Fermi level and usually have Schottky barrier when fB = 0.5 - 0.8 eV. To obtain Ohmic contact, make barrier very narrow very heavy doping (n+ or p+ ~ 1020 cm-3) adjacent to the metal. Al is a p dopant. 11/17/03 3.155J/6.152J 12 6
3. Step coverage, and 4. Patterning Step coverage is controlled by the deposition method Patterning method is controlled by the chemistry of the material Dep method Etch method Al-Si-Cu Sputter RIE in CCl4 or wet etch* in acetic/nitric acid W CVD etch or CMP poly-SI CVD Nitric acid P late, sputter Damascene CMP *undesirable for very small features ll/703 3.155J6.l52J Cu by damas cene process Cu problem: difficult to etch, also it reacts with Si degrades the operation of the transistors Solution: Damascene process for deposition: does not require etching. Make trenches, deposit plating base, then fill with electrodeposition and polish surface. The vias can be made simultaneously in a dual damascene process. Al can also be deposited by a damascene process(sputter and reflow to fill trenches) use diffusion barriers to prevent diffusion, e.g. TIN(made by CVD) ll/703 3.155J6.l52J
3. Step coverage, and 4. Patterning Step coverage is controlled by the deposition method; Patterning method is controlled by the chemistry of the material. Dep. method Etch method Al-Si-Cu Sputter RIE in CCl4 or wet etch* in acetic/nitric acid W CVD etch or CMP poly-Si CVD Nitric acid Cu P late , sputter Damascene, CMP *undesirable for very small features 11/17/03 3.155J/6.152J 13 Cu by damascene process Cu problem: difficult to etch; also it reacts with Si, degrades the operation of the transistors. Solution: Damascene process for deposition: does not require etching. Make trenches, deposit plating base, then fill with electrodeposition and polish surface. The vias can be made simultaneously in a dualdamascene process. Al can also be deposited by a damascene process (sputter and reflow to fill trenches). polish Cu dielectric barrier use diffusion barriers to prevent diffusion, e.g.TiN (made by CVD). 11/17/03 3.155J/6.152J 14 7
5. Stability: thermal and mechanical Thermal stability At elevated temperatures, metals can react with Si or SiO2 to produce unwanted phases, e. g silicides, eutectics or intermetallics This limits the maximum processing temperature (Typically quite low compared to temperatures needed for oxidation, dopant diffusion: hence the metal is done last Max temperatures Al on si 450°C barrier layers eg. PtSi, TiSi,, TiW, TIN 3.155J6.152J
5. Stability: thermal and mechanical Thermal stability: At elevated temperatures, metals can react with Si or SiO2 to produce unwanted phases, e.g. silicides, eutectics or intermetallics. This limits the maximum processing temperature (T typically quite low compared to temperatures needed for oxidation, dopant diffusion: hence the metal is done last). Max. temperatures: Al on Si 450˚C Solution: add ~1%Si to metal; use barrier layers eg. PtSi, TiSi2, TiW, TiN 11/17/03 3.155J/6.152J 17
Gate contacts Al cannot withstand the temperatures needed for MOSFET fabrication. Instead, gate contacts are made of Polysilicon, doped heavily,.or Silicides: For lower resistivity than poly Si Make by sputtering CVD, or by depositing metal on Si then reacting Silicide over poly-Si(polycide)on the gate takes advantage of the reliable Si/oxide inter face but with lower resistance Silicides can be made on gate, source and drain by self-aligned process C"salicide): the silicide forms only at the places where the metal contacts the silicon then the unreacted metal is removed Many possibilities WSi,, TaSi,, MoSi,, TiSi,, CoSi, All have different microstructures. thermal stabilities and reactivities ll/703 3.155J6.l52J 19 Mechanical stability As wafer is thermally cycled during processing packaging, mechanical stresses can build up due to thermal mismatch Deposited films, oxides etc also grow with internal stress. These stresses can cause delamination and void or hillock formation Mechanical properties of interconnect muterial Thermal modulus Hardness Melting material coefficient(C) Y/(1-1)(MPa) (kg mm) point (C) Al(111)23.1×10-° 1.143×10° 8.41×10-6 1.699×1081-14 TAI 123×10-6 660-750 Si(10026×10- 1.805×10° 1417 Si(1) 2.290×10° 0.55×10-6 083×10° 1700
11/17/03 3.155J/6.152J 20 11/17/03 3.155J/6.152J Gate contacts Al cannot withstand the temperatures needed for MOSFET fabrication. Instead, gate contacts are made of: Silicides Many possibilities WSi2, TaSi2, MoSi2, TiSi2 2 Several complex crystal structures may be possible in each system. 19 Polysilicon, doped heavily, …or ... : For lower resistivity than polySi. Make by sputtering, CVD, or by depositing metal on Si then reacting. Silicide over poly-Si (“polycide”) on the gate takes advantage of the reliable Si/oxide interface but with lower resistance Silicides can be made on gate, source and drain by self-aligned process (“salicide”): the silicide forms only at the places where the metal contacts the silicon, then the unreacted metal is removed. , CoSi All have different microstructures, thermal stabilities and reactivities. Mechanical stability As wafer is thermally cycled during processing & packaging, mechanical stresses can build up due to thermal mismatch. Deposited films, oxides etc. also grow with internal stress. These stresses can cause delamination and void or hillock formation. 10
Interface can delaminate Void can form if line is in tension metal can be extruded as hillocks througl racks in the overcoat outions control thermal cycling during processing, choose materials with compatible thermal expansion control film stress(by deposition method) use adhesion layer, eg that reacts with silica to form an oxide, making a chemical bond to the substrate ll/703 3.155J6.l52J Thermal Old IBM multi-chip module More than 30 layers ceramic green sheet Containing x, y lines and vias and 100 chips mounted with solder balls signals in and Optimal dielectric( no electrical breaks, robust ll/703 3.155J6.l52J
Thermal management in packaging: Old IBM multi-chip module More than 30 layers of ceramic “green sheet” Fired Containing x, y lines and vias and 100 chips mounted with solder balls x y vias Power, signals in and out How pick ceramic, conductors to co-fire without warp (thermal expansion), Optimal dielectric constant for speed, no electrical breaks, robust… And hermetically sealed with helium and heat sinks contacting each chip 11/17/03 3.155J/6.152J 24 12 Void can form if line is in tension. Dielectric Metal line Substrate Interface can delaminate In compression, metal can be extruded as ‘hillocks’ through cracks in the overcoat. Solutions: control thermal cycling during processing, or choose materials with compatible thermal expansion control film stress (by deposition method) use adhesion layer, eg that reacts with silica to form an oxide, making a chemical bond to the substrate. 11/17/03 3.155J/6.152J 21