3.155J/6.152JFal2003 CAP Massachusetts Institute of Technology POLY GATE MOSCAP PROCESS SUMMARY Lab session 1 1. 1 Lab Safety and Cleanroom Orientation 1.2 RCA ( ICL RC 1.3 Gate Oxidation Thermco Atmospheric Furnace(5D-FieldOx 1.4 Doped Polysilicon Deposition Thermco LPCVD(6A-Poly) 1.5 Anneal Thermco Atmospheric Furnace(5B-Anneal) Lab session 2 2. 1 Measure oxide and polysilicon thickness(UV1280 2.2 Etch oxide in BOE until de-wet (OxEtch-BOE) 2.3 HMDS, Photoresist Application, Postbake(SSI coater track) 2.4 Dry etch backside polysilicon( LAM490B) 2.5 Etch backside oxide in BOE until de-wet(OXEtch-BOE 2.6 Strip frontside resist with Matrix System One Stripper(Asher) ab session 3 3.1 HMDS, Photoresist Application, Pre-bake(SSI coater track 3.2 Exposure, Development, and Inspection(i-stepper), (SSl coater track),(optical microscope 3.3 Dry-etch polysilicon(LAM490B) 3. 4 Strip photoresist with Matrix System One Stripper(Asher) Testing T1 Device characterization: MOS Capacitor Determine oxide capacitance. Determine bulk dopant concentration Determine fixed interface charge T2 Sheet resistance measurement: Van der Pauw structure
3.155J / 6.152J Fall 2003 MOSCAP 1 Massachusetts Institute of Technology POLY GATE MOSCAP PROCESS SUMMARY Lab Session 1 1.1 Lab Safety and Cleanroom Orientation 1.2 RCA (ICL RCA) 1.3 Gate Oxidation Thermco Atmospheric Furnace (5D-FieldOx) 1.4 Doped Polysilicon Deposition Thermco LPCVD (6A-Poly) 1.5 Anneal Thermco Atmospheric Furnace (5B-Anneal) Lab Session 2 2.1 Measure oxide and polysilicon thickness (UV1280) 2.2 Etch oxide in BOE until de-wet (OxEtch-BOE) 2.3 HMDS, Photoresist Application, Postbake (SSI coater track) 2.4 Dry etch backside polysilicon (LAM490B) 2.5 Etch backside oxide in BOE until de-wet (OxEtch-BOE) 2.6 Strip frontside resist with Matrix System One Stripper (Asher) Lab Session 3 3.1 HMDS, Photoresist Application, Pre-bake (SSI coater track) 3.2 Exposure, Development, and Inspection (i-stepper), (SSI coater track), (optical microscope) 3.3 Dry-etch polysilicon (LAM490B) 3.4 Strip photoresist with Matrix System One Stripper (Asher) Testing T.1 Device characterization: MOS Capacitor Determine oxide capacitance. Determine bulk dopant concentration. Determine fixed interface charge. T.2 Sheet resistance measurement: Van der Pauw structure
3.155J/6.152 J Fall2003 MOSCAP MOSCAP LAB SESSION Gate Oxidation, Polysilicon Deposition and Anneal Location: ICL (2 floor, Building 39) Overview of lab session This first session will start with and introduction to the Integrated Circuits Lab(ICL) lab environment, as well as proper and safe working practices. The fabrication sequence will begin with a rigorous cleaning procedure that eliminates sources of wafer contamination and preserves the clean integrity of the furnaces. a-500 a gate oxide will be grown using a dry oxidation process. Immediately following the oxidation, the doped polysilicon gate layer will be deposited by chemical vapor deposition( LPCVD )to a target thickness of 2500 A. The deposited polysilicon ayer will be annealed to enhance an even distribution of dopants Lab objectives Review of lab safety and administrative procedures Introduction to cleanroom gowning and wafer-handling practices to avoid contamination Characterize basic physical and electrical characteristics of the starting n-type silicon substrates Complete growth and characterization of the gate oxide Complete growth of the gate polysilicon Instruction on the following major pieces of lab equipment Semifab RCA Cleaning Station Thermco Atmospheric Furnace(5D-FieldOx) Thermco Low Pressure Furnace(6A-Poly) Thermco Atmospheric Furnace(5B-anneal) Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at http://www-mtl.mitedu/mtihome/3mfab/soP.html Lab procedures: 1. Lab Safety and Cleanroom Orientation Read the sections on lab safety and code of conduct before attending lab session 2. RCA Wafer Clean Follow the SOP for the Semifab RCA Cleaning Station 3. Gate Oxidation Note: This step must be immediately preceded by RCa clean Approximately 500 A will be grown using a dry oxidation process at 1000 C. Follow the SOP for the Thermo Atmospheric Furnace(5D-FieldOx) using recipe 6. 152 GATEOX 500A"with an interval time of 1 hour for the step of dry oxidation 4. Doped Polysilicon Deposition Note: this step must immediately follow the gate oxidation About 2500 A of phosphorus-doped polysilicon will be deposited by LPCVD in the Thermco Furnace(6A-Poly) The deposition rate is fixed at -30 A/min 5. Anneal The deposited polysilicon gate layer will be annealed at 950C for 12 minutes in a nitrogen ambient to enhance an even distribution of phosphorus dopants. Follow the SOP for the Thermo Atmospheric Furnace(5B-anneal)
3.155J / 6.152J Fall 2003 MOSCAP 2 MOSCAP LAB SESSION 1 Gate Oxidation, Polysilicon Deposition and Anneal Location: ICL (2nd floor, Building 39) Overview of Lab Session: This first session will start with and introduction to the Integrated Circuits Lab (ICL) lab environment, as well as proper and safe working practices. The fabrication sequence will begin with a rigorous cleaning procedure that eliminates sources of wafer contamination and preserves the clean integrity of the furnaces. A ~500 Å gate oxide will be grown using a dry oxidation process. Immediately following the oxidation, the doped polysilicon gate layer will be deposited by chemical vapor deposition (LPCVD) to a target thickness of 2500 Å. The deposited polysilicon layer will be annealed to enhance an even distribution of dopants. Lab Objectives: • Review of lab safety and administrative procedures • Introduction to cleanroom gowning and wafer-handling practices to avoid contamination • Characterize basic physical and electrical characteristics of the starting n-type silicon substrates • Complete growth and characterization of the gate oxide • Complete growth of the gate polysilicon • Instruction on the following major pieces of lab equipment: • Semifab RCA Cleaning Station • Thermco Atmospheric Furnace (5D-FieldOx) • Thermco Low Pressure Furnace (6A-Poly) • Thermco Atmospheric Furnace (5B-anneal) Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at: http://www-mtl.mit.edu/mtlhome/3Mfab/sop.html Lab Procedures: 1. Lab Safety and Cleanroom Orientation Read the sections on lab safety and code of conduct before attending lab session. 2. RCA Wafer Clean Follow the SOP for the Semifab RCA Cleaning Station. 3. Gate Oxidation Note: This step must be immediately preceded by RCA clean! Approximately 500 Å will be grown using a dry oxidation process at 1000 C. Follow the SOP for the Thermco Atmospheric Furnace (5D-FieldOx) using recipe "6.152 GATEOX 500A" with an interval time of 1 hour for the step of dry oxidation. 4. Doped Polysilicon Deposition Note: this step must immediately follow the gate oxidation. About 2500 Å of phosphorus-doped polysilicon will be deposited by LPCVD in the Thermco Furnace (6A-Poly). The deposition rate is fixed at ~30 A/min. 5. Anneal The deposited polysilicon gate layer will be annealed at 9500 C for 12 minutes in a nitrogen ambient to enhance an even distribution of phosphorus dopants. Follow the SOP for the Thermco Atmospheric Furnace (5B-anneal)
3.155J/6.152 J Fall2003 MOSCAP Pre-Lab Questions 1. What contaminants does the rCa clean remove? What is the purpose of the HF dip in the rca clean? 2. Why is dry oxidation used to grow the gate oxide? 3. From the oxide growth chart in the Appendix, predict the gate oxide thickness after the oxidation 4. From the oxide color chart in the Appendix, what color would one expect the gate oxide to appear 5. What are the advantages of using polysilicon rather than aluminum for the gate electrode? 6. What is the by-product of the polysilicon deposition? What controls the deposition rate (transfer of SiH4, reaction at the surface of the substrate, or removal of the by-product)? 7. Sketch a cross section of the wafer after this lab session
3.155J / 6.152J Fall 2003 MOSCAP 3 Pre-Lab Questions: 1. What contaminants does the RCA clean remove? What is the purpose of the HF dip in the RCA clean? 2. Why is dry oxidation used to grow the gate oxide? 3. From the oxide growth chart in the Appendix, predict the gate oxide thickness after the oxidation. 4. From the oxide color chart in the Appendix, what color would one expect the gate oxide to appear? 5. What are the advantages of using polysilicon rather than aluminum for the gate electrode? 6. What is the by-product of the polysilicon deposition? What controls the deposition rate (transfer of SiH4, reaction at the surface of the substrate, or removal of the by-product)? 7. Sketch a cross section of the wafer after this lab session
3.155J/6.152 J Fall2003 MOSCAP MOSCAP LAB SESSION 2 Back-side Strip Location: ICL (2 floor, Building 39) Overview of lab session The first step of this lab session will be to characterize the oxide and polysilicon films deposited in lab session 1. The main processing taking place in this lab session will be the removal of the oxide and polysilicon layers from the back side of the wafers. This will allow electrical contact to the back side of the wafer. The wafers will be coated with a photoresist solution using an automatic coating system which has several modules operating in a pipelined fashion. The first module treats each wafer with Hexamethyldisilazane(HMDs)vapor, an adhesion promoter. Next, a photoresist solution is dispensed onto the wafer and evenly distributed by a spin-on technique Finally, the wafer is baked to expel solvents from the photoresist. Since the wafers will not be patterned photolithographically, the wafers will be post-baked directly(rather than pre-baked exposed, and then post-baked) to harden the resist into a protective masking layer. The back sides of the wafers will be etched dry-etched in He/Cl2 plasma. Next, the oxide will be wet-etched in buffered oxide etch(BOE), a solution of hydrofluoric acid. Finally, the photoresist will be stripped by oxygen plasma etch Lab Objectives: Complete characterization of Oxide and Polysilicon films grown in Lab Session 1 Remove oxide and polysilicon films from back side of wafers Instruction on the following pieces of lab equipment KLA Tencor UV1280 Film Thickness Measurement System SSI Coater Track LAM 490B Plasma Etcher Oxide etch sink Matrix 106 System One Stripper Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at: http://www-mtl.mitedu/mtlhome/3mfab/sop.html Lab procedure 1. Characterize Oxide and Polysilicon deposited in Lab session 1 Measure the oxide and polysilicon thickness using the UV1280 Note: An oxide color chart is enclosed in the Appendix. The color chart assumes perpendicular illumination and viewing of wafer surface under white fluorescent lighting 2. Etch oxide in boe (Oxide etch sink Using the Oxide Etch Sink, etch the native oxide on the polisilicon surface of the wafer in Buffered-Oxide-Etch(BOE). The etch rate for bOE is about 1000 A/min the thickness of the native oxide is around 200 a so estimate the approximate etch time required. When the BOE etch is complete, the BOE should'de-wet'or bead up off the wafer. After completing etch, rinse thoroughly with DI water and spin dry Overall reaction for etching Sio2 with BOE SiO2+ 6HF == H2+ SiF6+ 2H2O where a buffering agent, ammonium fluoride(NH4 F), is added to maintain HF concentration and to control pH to minimize photoresist attack) NH4F <== NH3 HF
3.155J / 6.152J Fall 2003 MOSCAP 4 MOSCAP LAB SESSION 2 Back-side Strip Location: ICL (2nd floor, Building 39) Overview of Lab Session: The first step of this lab session will be to characterize the oxide and polysilicon films deposited in lab session 1. The main processing taking place in this lab session will be the removal of the oxide and polysilicon layers from the back side of the wafers. This will allow electrical contact to the back side of the wafer. The wafers will be coated with a photoresist solution using an automatic coating system which has several modules operating in a pipelined fashion. The first module treats each wafer with Hexamethyldisilazane (HMDS) vapor, an adhesion promoter. Next, a photoresist solution is dispensed onto the wafer and evenly distributed by a spin-on technique. Finally, the wafer is baked to expel solvents from the photoresist. Since the wafers will not be patterned photolithographically, the wafers will be post-baked directly (rather than pre-baked, exposed, and then post-baked) to harden the resist into a protective masking layer. The back sides of the wafers will be etched dry-etched in He/Cl2 plasma. Next, the oxide will be wet-etched in buffered oxide etch (BOE), a solution of hydrofluoric acid. Finally, the photoresist will be stripped by oxygen plasma etch. Lab Objectives: • Complete characterization of Oxide and Polysilicon films grown in Lab Session 1. • Remove oxide and polysilicon films from back side of wafers. • Instruction on the following pieces of lab equipment • KLA Tencor UV1280 Film Thickness Measurement System • SSI Coater Track • LAM 490B Plasma Etcher • Oxide Etch Sink • Matrix 106 System One Stripper Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at: http://www-mtl.mit.edu/mtlhome/3Mfab/sop.html Lab Procedures: 1. Characterize Oxide and Polysilicon deposited in Lab session 1. Measure the oxide and polysilicon thickness using the UV1280. Note: An oxide color chart is enclosed in the Appendix. The color chart assumes perpendicular illumination and viewing of wafer surface under white fluorescent lighting. 2. Etch oxide in BOE. (Oxide etch sink) Using the Oxide Etch Sink, etch the native oxide on the polisilicon surface of the wafer in Buffered-Oxide-Etch (BOE). The etch rate for BOE is about 1000 Å/min. The thickness of the native oxide is around 200 Å so estimate the approximate etch time required. When the BOE etch is complete, the BOE should ‘de-wet’ or bead up off the wafer. After completing etch, rinse thoroughly with DI water and spin dry. Overall reaction for etching SiO2 with BOE: SiO2 + 6HF ==> H2 + SiF6 + 2H2O where a buffering agent, ammonium fluoride (NH4F), is added to maintain HF concentration and to control pH (to minimize photoresist attack): NH4F NH3 + HF
3.155J/6.152 J Fall2003 CAP NOTE: BOE contains a high concentration of hydrofluoric acid(HF). Be aware of the angers of handling HF! 3. Coat frontside of wafers with blanket photoresist and bake Follow the SoP for the SSI Coater Track, using the following three modules HMDS module: treatment promotes adhesion of photoresist coating module: photoresist will be dispensed and spun on for -1 micron thickness bake module: at 95C for 60 s on hot plate 4. Dry-etch backside polysilicon in He/Cl2 plasma Use the LAM 490B with recipe"BACKSIDE POLY (5KA)"to etch the exposed polysilicon on the backside of the wafer. The wafers will be loaded into the machine upside down Take care handling the wafers to avoid marring the front side Based on you previous measurements of polysilicon thickness, estimate the appropriate etch time required 5. Etch backside gate oxide in BOE until de-wet (Oxide etch sink) Using the Oxide Etch Sink, etch the exposed oxide on the back side of the wafer in Buffered-Oxide-Etch(BOE). The etch rate for BOE is about 1000 A/min. Based on your previous measurements of oxide thickness, estimate the approximate etch time required When the boe etch is complete, the boE should'de-wet or bead up off the wafer. After completing etch, rinse thoroughly with DI water and spin dry NOTE: BOE contains a high concentration of hydrofluoric acid(HF). Be aware of the dangers of handling HF 6. Strip photoresist with the Matrix System One Stripper(Asher) This is an oxygen plasma etch Pre-lab questions 1. Why is HMDS applied to the wafers before photoresist application? 2. Why is BOE particularly dangerous? How should one be gowned when handling BOE? 3. What is the purpose of Hgf in BOE? 4. Sketch a cross-section of the wafer after the processing in this session
3.155J / 6.152J Fall 2003 MOSCAP 5 NOTE: BOE contains a high concentration of hydrofluoric acid (HF). Be aware of the dangers of handling HF! 3. Coat frontside of wafers with blanket photoresist and bake. Follow the SOP for the SSI Coater Track, using the following three modules • HMDS module: treatment promotes adhesion of photoresist • coating module: photoresist will be dispensed and spun on for ~1 micron thickness • bake module: at 95 C for 60 s on hot plate 4. Dry-etch backside polysilicon in He/Cl2 plasma. Use the LAM 490B with recipe "BACKSIDE POLY (5KA)" to etch the exposed polysilicon on the backside of the wafer. The wafers will be loaded into the machine upside down. Take care handling the wafers to avoid marring the front side. Based on you previous measurements of polysilicon thickness, estimate the appropriate etch time required. 5. Etch backside gate oxide in BOE until de-wet. (Oxide etch sink) Using the Oxide Etch Sink, etch the exposed oxide on the back side of the wafer in Buffered-Oxide-Etch (BOE). The etch rate for BOE is about 1000 Å/min. Based on your previous measurements of oxide thickness, estimate the approximate etch time required. When the BOE etch is complete, the BOE should ‘de-wet’ or bead up off the wafer. After completing etch, rinse thoroughly with DI water and spin dry. NOTE: BOE contains a high concentration of hydrofluoric acid (HF). Be aware of the dangers of handling HF! 6. Strip photoresist with the Matrix System One Stripper (Asher) This is an oxygen plasma etch. Pre-lab questions: 1. Why is HMDS applied to the wafers before photoresist application? 2. Why is BOE particularly dangerous? How should one be gowned when handling BOE? 3. What is the purpose of NH4F in BOE? 4. Sketch a cross-section of the wafer after the processing in this session
155J/6.152JFal2003 MOSCAP MOSCAP LAB SESSION 3 Photolithography and Gate Patterning Location: ICL (2 floor, Building 39) Overview of lab session In this lab session, photolithography will be used to transfer an image from a mask to the wafer Wafers will be coated with photoresist on the sSI track, similar to the photoresist application step in Lab Session 2, except that wafers will be pre-baked. The pattern will be transferred from a mask to the wafer using the Nikon NSR2005i9 Wafer Stepper( i-stepper), a projection aligner The photoresist in the clear fields of the mask is exposed to UV light, and resist in these areas is removed when the wafer is developed. Finally, the wafer is post-baked to improve adhesion Using the photoresist as an etch mask, the polysilicon will be dry-etched using He/Cl2 plasma After this step, the photoresist will be ashed, and the process is completed Lab objectives Introduction to photolithographic process and procedures Patterning of polysilicon gate electrode Instruction on the following pieces of equipment SSI Coater Track Nikon NSR2005i9 Wafer Stepper(i-stepper LAM 490B Plasma Etcher Matrix 106 System One Stripper Optical Microscope Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at: http://www-mtl.mitedw/mtihome/3mfab/sop.html ab procedures. 1. HMDS, photoresist depostion, and pre-bake Follow the SOP for the SSI Coater Track, using the following modules In-line HMDs treatment Spin-on module: standard dispense for -1 micron thickness Pre-bake module: 95c on hot plate 2. Exposure, development and inspection Refer to Appendix for mask schematics Use the l-stepper to transfer mask pattern to wafers Use control wafer to make a'focus-expo' grid-a matrix of various focal lengths and Develop this wafer using the following modules of the SSI Coater Track Post-exposure bake Develop Post-bake Inspect developed control wafer with optical microscope and determine optimal focal length and exposure time Use these settings for exposure of device wafers Develop device wafers using the following modules of the SSl Coater Track Post-exposure bake Develop Postbake Inspect wafers visually with optical microscope
3.155J / 6.152J Fall 2003 MOSCAP 6 MOSCAP LAB SESSION 3 Photolithography and Gate Patterning Location: ICL (2nd floor, Building 39) Overview of Lab Session: In this lab session, photolithography will be used to transfer an image from a mask to the wafer. Wafers will be coated with photoresist on the SSI track, similar to the photoresist application step in Lab Session 2, except that wafers will be pre-baked. The pattern will be transferred from a mask to the wafer using the Nikon NSR2005i9 Wafer Stepper (i-stepper), a projection aligner. The photoresist in the clear fields of the mask is exposed to UV light, and resist in these areas is removed when the wafer is developed. Finally, the wafer is post-baked to improve adhesion. Using the photoresist as an etch mask, the polysilicon will be dry-etched using He/Cl2 plasma. After this step, the photoresist will be ashed, and the process is completed. Lab Objectives: • Introduction to photolithographic process and procedures. • Patterning of polysilicon gate electrode. • Instruction on the following pieces of equipment: • SSI Coater Track • Nikon NSR2005i9 Wafer Stepper (i-stepper) • LAM 490B Plasma Etcher. • Matrix 106 System One Stripper • Optical Microscope Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at: http://www-mtl.mit.edu/mtlhome/3Mfab/sop.html Lab Procedures: 1. HMDS, photoresist depostion, and pre-bake. Follow the SOP for the SSI Coater Track, using the following modules: • In-line HMDS treatment • Spin-on module: standard dispense for ~1 micron thickness • Pre-bake module: 95 C on hot plate. 2. Exposure, development and inspection Refer to Appendix for mask schematics. Use the I-stepper to transfer mask pattern to wafers. • Use control wafer to make a ‘focus-expo’ grid --- a matrix of various focal lengths and exposure times. • Develop this wafer using the following modules of the SSI Coater Track: Post-exposure bake Develop Post-bake • Inspect developed control wafer with optical microscope and determine optimal focal length and exposure time. • Use these settings for exposure of device wafers . • Develop device wafers using the following modules of the SSI Coater Track: Post-exposure bake Develop Postbake • Inspect wafers visually with optical microscope
3.155J/6.152 J Fall2003 MOSCAP 3. Dry-etch polysilicon in He/Cl2 plasma Use the LAM490B to etch exposed gate polysilicon that is not protected by photoresist Use recipe"POLY EP", This recipe feautres automatic endpoint detection From the etch time, calculate the average etch rate. Inspect wafers visually with optical microscope 4. Strip photoresist with the Matrix System One Stripper(Asher Pre-lab questions 1. Describe the various alignment marks on the reticle 2. Explain the difference between isotropic and anisotropic etch characteristics 3. What chemical is used to etch the polysilicon? Is this an isotropic or anisotropic etch? 4. Sketch the cross-section taken through the gate of a device MOSCAP Testing Location: ICL, EML (5 floor, Building 39) Overview of lab session: This lab session will take place in the Exploratory Materials Laboratory(EML). Electrical testing will be performed to characterize materials and device performance Lab object Introduce electrical testing instruments and procedures Characterize device performance and materials Relate device characteristics to fabrication process Lab procedures: 1. Device Characterization: MOS Capacitor The following devices will be measured 1)500 X 500 um cap, with anneal 2)200 X 200 um" cap, with anneal Follow instructions(in SOP for test station for use of HP-4061A system to perform C-V measurement(see appendix)on MOS capacitor. The gate electrode is probed, along with the backside of the substrate At high frequency(100 kHz), the result should be similar to this cv curve for an aluminum gate MOS structure
3.155J / 6.152J Fall 2003 MOSCAP 7 3. Dry-etch polysilicon in He/Cl2 plasma. • Use the LAM490B to etch exposed gate polysilicon that is not protected by photoresist. Use recipe "POLY EP".; This recipe feautres automatic endpoint detection. From the etch time, calculate the average etch rate. • Inspect wafers visually with optical microscope. 4. Strip photoresist with the Matrix System One Stripper (Asher) Pre-lab questions: 1. Describe the various alignment marks on the reticle. 2. Explain the difference between isotropic and anisotropic etch characteristics. 3. What chemical is used to etch the polysilicon? Is this an isotropic or anisotropic etch? 4. Sketch the cross-section taken through the gate of a device. MOSCAP Testing Location: ICL, EML (5nd floor, Building 39) Overview of Lab Session: This lab session will take place in the Exploratory Materials Laboratory (EML). Electrical testing will be performed to characterize materials and device performance. Lab Objectives: • Introduce electrical testing instruments and procedures • Characterize device performance and materials • Relate device characteristics to fabrication process Lab Procedures: 1. Device Characterization: MOS Capacitor The following devices will be measured: 1) 500 x 500 µm2 cap, with anneal 2) 200 x 200 µm2 cap, with anneal Follow instructions (in SOP for test station ) for use of HP-4061A system to perform C-V measurement (see appendix) on MOS capacitor. The gate electrode is probed, along with the backside of the substrate. At high frequency (100 kHz), the result should be similar to this CV curve for an aluminum gate MOS structure
3.155J/6.152 J Fall2003 CAP C-V Curve for MOS Capacitor 60 140 rmi, = 50pF I A. Oxide Capacitance: Cox All capacitance values with are area normalized capacitances: e.g. C=Ea a and From the accumulation capacitance C=AC C=-or lax Calculate tox and compare with measured values from UV1280 of gate oxide thickness taken in Lab session 2 B Bulk Dopant Concentration: Np From the high-frequency inversion capacitance, the bulk dopant concentration can be calculated
3.155J / 6.152J Fall 2003 MOSCAP 8 A. Oxide Capacitance: Cox All capacitance values with * are area normalized capacitances; e.g. ox ox ox t A C ε = and ox ox ox t C ε = * . From the accumulation capacitance: * Cacc = ACox ox ox ox t C ε = * Calculate tox and compare with measured values from UV1280 of gate oxide thickness taken in Lab Session 2. B. Bulk Dopant Concentration: ND From the high-frequency inversion capacitance, the bulk dopant concentration can be calculated
3.155J/6.152 J Fall2003 CAP here Cs semiconductor capacitance gEsN 22 and C Fixed Interface Charge: QF Calculate the capacitance at flatband voltage(The condition where the surface concentration of electrons is equal to that in the bulk k7 g8 Find the flatband voltage VFB corresponding to CFB from the C-V curve Calculate approximately the fixed charge at the Si/Sio2 interface from the theoretical expression for flatband voltage Q n 2. Sheet Resistance: Van der Pauw Structure The Van der Pauw structure is used to measure sheet resistance. the structure consists of an area of material contacted at each corner. Rsquare=(TT/n 2)(V/I)Ohms/square Van der Pauw further showed that by taking voltage measurements from adjacent leads when current is forced through the other 2 leads, then rotating the lead positions by 90°,, any asymmetry in the structure could be corrected for by using a mathematical
3.155J / 6.152J Fall 2003 MOSCAP 9 ( ) * * * * * min ox S ox S C C C C C + = where Cs = semiconductor capacitance: ( ) F S D S q N C Φ = 2 2 * ε and Φ = i D F n N q kT ln C. Fixed Interface Charge: QF Calculate the capacitance at flatband voltage (The condition where the surface concentration of electrons is equal to that in the bulk.). ox S D FB q N kT C C ε * 2 * 1 1 + = Find the flatband voltage VFB corresponding to CFB from the C-V curve. Calculate approximately the fixed charge at the Si/SiO2 interface from the theoretical expression for flatband voltage. = Φ − * ox F FB MS C Q V − Φ = ni N q kT ni N q kT D C MS ln ln = C D N N q kT ln 2. Sheet Resistance: Van der Pauw Structure The Van der Pauw structure is used to measure sheet resistance. The structure consists of an area of material, contacted at each corner. Rsquare = (π/ln 2) (V/I) Ohms/square . Van der Pauw further showed that by taking voltage measurements from adjacent leads when current is forced through the other 2 leads, then rotating the lead positions by 90°, any asymmetry in the structure could be corrected for by using a mathematical
3.155J/6.152 J Fall2003 MOSCAP function. The structures to be tested on the mask are symmetrical by design, so do need to be corrected. Still, the average of the two measurements yields a better estir the sheet resistance of the underlying material Rsquare=(4.53/2)[(VcD/AB)+(VBc/aD)]Ohms/square To measure the sheet resistance using the Van der Pauw structure, use program PPOLYVDP. Setup of leads for both are as follows SMU2 current Source SMU 1 15] VM 1 Voltage Tap [21 VM 2 ge lap Average resistivity can then be determined simply by multiplying the measured sheet resistance by the thickness of the polysilicon layer Physical Constants: es=1.05*102(F/cm) eoX=345*10(F/c q=1.6X10c kt/q=.026 V Nc=286×1019#/cn ni=1010#(cm <Appendices
3.155J / 6.152J Fall 2003 MOSCAP 10 function. The structures to be tested on the mask are symmetrical by design, so do not need to be corrected. Still, the average of the two measurements yields a better estimate of the sheet resistance of the underlying material. Rsquare = (4.53/2) [(VCD/IAB) + (VBC/IAD)] Ohms/square . To measure the sheet resistance using the Van der Pauw structure, use program PPOLYVDP. Setup of leads for both are as follows: SMU 1 -- Current Source -- [7] SMU 2 -- Ground -- [15] VM 1 -- Voltage Tap -- [21] VM 2 -- Voltage Tap -- [5] Average resistivity can then be determined simply by multiplying the measured sheet resistance by the thickness of the polysilicon layer. Physical Constants: es=1.05*10-12 (F/cm) eox=3.45*10-13 (F/cm) q = 1.6 x 10-19 C kt/q = .026 V Nc = 2.86 x 1019 #/cm3 ni = 1010 #/cm3
