expressed in terms of the filter time constant and also the ratio of the filter cutoff frequency, fc,, to the ADC sampling frequency, fs SINGLE-POLE FILTER SETTLING TIME TO REQUIRED ACCURACY RESOLUTION, LSB (%FS) H OF TIME fe2/fs OF BITS CONSTANTS 1563 4.16 0.67 0.391 5.55 0.89 00977 6.9 1.11 0246802 0.0244 832132 970 0.00153 1.77 0.00038 12.48 2.00 0.000095 13.86 2.22 0.000024 15.25 Figure 6.10 As an example, assume that the adc is a 12-bit one sampling at 100kSPS. From the table in Figure 6.10, 8.32 time constants are required for the filter to settle to 12-bit accuracy, and ≥132,orfe2≥132kSPS While this filter will help prevent wideband noise from entering the SHA, it does not prouide the same function as the antialiasing filters at the input of each channel The above analysis assumes that the multiplexer/PGA combined settling time is significantly less than the filter settling time. If this is not the case, then the filter cutoff frequency must be larger, and in most cases it should be left out entirely in favor of per-channel filters SHA AND ADC SETTLING TIME REQUIREMENTS IN MULTIPLEXED APPLICATIONS We have discussed the importance of the fullscale settling time of the multiplexer/PGAfilter combination, but what is equally important is the ability of the adc to acquire the final value of the step voltage input signal to the required accuracy. Failure of any link in the signal chain to settle will result in dc crosstalk between adjacent channels and loss of accuracy If the data acquisition system uses a separate SHA and ADC, then the key specification to examine is the Sha acquisition time, which is usually specified as a the amount of time required to acquire a fullscale input signal to 0. 1% accuracy(10-bits)or.01% accuracy(139 expressed in terms of the filter time constant and also the ratio of the filter cutoff frequency, fc2,to the ADC sampling frequency, fs . SINGLE-POLE FILTER SETTLING TIME TO REQUIRED ACCURACY Figure 6.10 As an example, assume that the ADC is a 12-bit one sampling at 100kSPS. From the table in Figure 6.10, 8.32 time constants are required for the filter to settle to 12-bit accuracy, and fc fs 2 ³ 132 . , or fc2 ³ 132kSPS. While this filter will help prevent wideband noise from entering the SHA, it does not provide the same function as the antialiasing filters at the input of each channel. The above analysis assumes that the multiplexer/PGA combined settling time is significantly less than the filter settling time. If this is not the case, then the filter cutoff frequency must be larger, and in most cases it should be left out entirely in favor of per-channel filters. SHA AND ADC SETTLING TIME REQUIREMENTS IN MULTIPLEXED APPLICATIONS We have discussed the importance of the fullscale settling time of the multiplexer/PGA/filter combination, but what is equally important is the ability of the ADC to acquire the final value of the step voltage input signal to the required accuracy. Failure of any link in the signal chain to settle will result in dc crosstalk between adjacent channels and loss of accuracy. If the data acquisition system uses a separate SHA and ADC, then the key specification to examine is the SHA acquisition time, which is usually specified as a the amount of time required to acquire a fullscale input signal to 0.1% accuracy (10-bits) or 0.01% accuracy (13-