SECTION 6 MULTICHANNEL APPLICATIONS Data Acquisition System Considerations Multiplexing Filtering Considerations for Data Acquisition Systems SHA and ADC Settling Time Requirements in Multiplexed Applications Complete Data Acquisition Systems on a Chip Multiplexing into Sigma-Delta ADCs Simultaneous Sampling Systems Data Distribution Systems using Multiple DACS
1 SECTION 6 MULTICHANNEL APPLICATIONS Data Acquisition System Considerations Multiplexing Filtering Considerations for Data Acquisition Systems SHA and ADC Settling Time Requirements in Multiplexed Applications Complete Data Acquisition Systems on a Chip Multiplexing into Sigma-Delta ADCs Simultaneous Sampling Systems Data Distribution Systems using Multiple DACs
SECTION 6 MULTICHANNEL APPLICATIONS Walt Kester. Wes Freeman DATA ACQUISITION SYSTEM CONFIGURATIONS There are many applications for data acquisition systems in measurement and process control. All data acquisition applications involve digitizing analog signals for analysis using ADCs. In a measurement application, the ADC is followed by a digital processor which performs the required data analysis. In a process control application, the process controller generates feedback signals which typically must be converted back into analog form using a dac Although a single adc digitizing a single channel of analog data constitutes a data acquisition system, the term data acquisition generally refers to multi-channel systems. If there is feedback from the digital processor, DACs may be required to convert the digital responses into analog. This process is often referred to as data distribution Figure 6.1 shows a data acquisition/distribution process control system where ead channel has its own dedicated ADC and DAC. an alternative configuration is shown in Figure 6.2, where analog multiplexers and demultiplexers are used with a single ADC and DAC. In most cases, especially where there are many channels, this configuration provides an economical alternative DATA ACQUISITION SYSTEM USING ADC/ DAC PER CHANNEL PROCESS CONTROLLER +2 DAC ADC PROCESS DAC Figure 6.1
2 SECTION 6 MULTICHANNEL APPLICATIONS Walt Kester, Wes Freeman DATA ACQUISITION SYSTEM CONFIGURATIONS There are many applications for data acquisition systems in measurement and process control. All data acquisition applications involve digitizing analog signals for analysis using ADCs. In a measurement application, the ADC is followed by a digital processor which performs the required data analysis. In a process control application, the process controller generates feedback signals which typically must be converted back into analog form using a DAC. Although a single ADC digitizing a single channel of analog data constitutes a data acquisition system, the term data acquisition generally refers to multi-channel systems. If there is feedback from the digital processor, DACs may be required to convert the digital responses into analog. This process is often referred to as data distribution. Figure 6.1 shows a data acquisition/distribution process control system where each channel has its own dedicated ADC and DAC. An alternative configuration is shown in Figure 6.2, where analog multiplexers and demultiplexers are used with a single ADC and DAC. In most cases, especially where there are many channels, this configuration provides an economical alternative. DATA ACQUISITION SYSTEM USING ADC / DAC PER CHANNEL Figure 6.1
DATA ACQUASITION SYSTEM USING ANALOG MULTIPLEXING/DEMULTIPLEXING AND SINGLE ADC/ DAC DAC CONTROLLER ADC ANALOG PROCESS ANALOG Figure 6.2 There are many tradeoffs involved in designing a data acquisition system Issues such as filtering, amplification, multiplexing, demultiplexing, sampling frequency and partitioning must be resolved. MULTIPLEXING Multiplexing is a fundamental part of a data acquisition system. Multiplexers and switches are examined in more detail in Reference 1. but a fundamental understanding is required to design a data acquisition system. a simplified diagram of an analog multiplexer is shown in Figure 6.3. The number of input channels typically ranges from 4 to 16, and the devices are generally fabricated on CMOs processes. Some multiplexers have internal channel-address decoding logic and registers, while with others, these functions must be performed externally. Unused multiplexer inputs must be grounded or severe loss of system accuracy may result The key specifications are switching time, on-resistance, on-resistance modulation and off-channel isolation(crosstalk Multiplexer switching time ranges from about 50ns to over lus, on-resistance from 25ohms to several hundred ohms, and off channel isolation from 50 to 90dB. The use of trench isolation has eliminated latch up in multiplexers while yielding improvements in speed at low supply voltages
3 DATA ACQUASITION SYSTEM USING ANALOG MULTIPLEXING / DEMULTIPLEXING AND SINGLE ADC / DAC Figure 6.2 There are many tradeoffs involved in designing a data acquisition system. Issues such as filtering, amplification, multiplexing, demultiplexing, sampling frequency, and partitioning must be resolved. MULTIPLEXING Multiplexing is a fundamental part of a data acquisition system. Multiplexers and switches are examined in more detail in Reference 1, but a fundamental understanding is required to design a data acquisition system. A simplified diagram of an analog multiplexer is shown in Figure 6.3. The number of input channels typically ranges from 4 to 16, and the devices are generally fabricated on CMOS processes. Some multiplexers have internal channel-address decoding logic and registers, while with others, these functions must be performed externally. Unused multiplexer inputs must be grounded or severe loss of system accuracy may result. The key specifications are switching time, on-resistance, on-resistance modulation, and off-channel isolation (crosstalk). Multiplexer switching time ranges from about 50ns to over 1µs, on-resistance from 25ohms to several hundred ohms, and offchannel isolation from 50 to 90dB. The use of trench isolation has eliminated latchup in multiplexers while yielding improvements in speed at low supply voltages
SIMPLIFIED DIAGRAM OF A TYPICAL ANALOG MULTIPLEXER CH ADDRESS CLOCK DECODER BUFFER, SHA, PGA, ADC ANALOG RL MUX Figure 6.3 MULTIPLEXER KEY SPECIFICATIONS Switching Time: 50ns to >lus On-Resistance: 25o to hundreds of os On-Resistance Modulation(Ron change with signal level Off-Channel isolation 50 to 90 dB Overvoltage Protection Figure 6.4
4 SIMPLIFIED DIAGRAM OF A TYPICAL ANALOG MULTIPLEXER Figure 6.3 MULTIPLEXER KEY SPECIFICATIONS Switching Time: 50ns to >1 s On-Resistance: 25 to hundreds of ’s On-Resistance Modulation (Ron change with signal level) Off-Channel Isolation: 50 to 90 dB Overvoltage Protection Figure 6.4
WHAT'S NEW IN MULTIPLEXERS? Trench Isolation gives high speed, latch-up protection, and low voltage operation ADG511, ADG512, ADG513: +3. 3v, +5V,#5V specified Ron<509@±5V Switching Time: <200ns@+5V ADG411, ADG412, ADG413:+15v, +12V specified Ron<3592@ ±15 V Switching Time:<150ns@±15V ADG508F, ADG509F, ADG528F:+15V specified Ron 300Q Switching Time:≤250ns Fault-Protection on Inputs and Outputs Figure 6.5 Multiplexer on-resistance is generally slightly dependent on the signal level(often called Ron modulation). This will cause signal distortion if the multiplexer must drive a load resistance, therefore the multiplexer output should therefore be isolated from the load with a suitable buffer amplifier. a separate buffer is not required if the multiplexer drives a high input impedance, such as a Pga, sha or ADC-but beware! Some SHAs and ADCs draw high frequency pulse current at their sampling rate and cannot tolerate being driven by an unbuffered multiplexer. a detailed analysis of multiplexers can be found in Reference 1, Section 8, or Reference 2, Section 2 An M-channel multiplexed data acquisition system is shown in Figure 6.6. The multiplexer output drives a Pga whose gain can be adjusted on a per- channel basis depending on the channel signal level. This ensures that all channels utilize the full dynamic range of the ADC. The PGa gain is changed at the same time as the multiplexer is switched to a new channel. The AdC Convert Command is applied fter the multiplexer and the pga have settled to the required accuracy(ILSB). The maximum sampling frequency(when switching between channels)is limited by the multiplexer switching time tmux, the Pga settling time tmga, and the adc conversion time tony as shown in the formula
5 WHAT’S NEW IN MULTIPLEXERS? Trench Isolation gives high speed, latch-up protection, and lowvoltage operation ADG511, ADG512, ADG513: +3.3V, +5V, 5V specified Ron < 50 @ 5V Switching Time: <200ns @ 5V ADG411, ADG412, ADG413: 15V, +12V specified Ron < 35 @ 15V Switching Time: <150ns @ 15V ADG508F, ADG509F, ADG528F: 15V specified Ron < 300 Switching Time: < 250ns Fault-Protection on Inputs and Outputs Figure 6.5 Multiplexer on-resistance is generally slightly dependent on the signal level (often called Ron modulation). This will cause signal distortion if the multiplexer must drive a load resistance, therefore the multiplexer output should therefore be isolated from the load with a suitable buffer amplifier. A separate buffer is not required if the multiplexer drives a high input impedance, such as a PGA, SHA or ADC - but beware! Some SHAs and ADCs draw high frequency pulse current at their sampling rate and cannot tolerate being driven by an unbuffered multiplexer. A detailed analysis of multiplexers can be found in Reference 1, Section 8, or Reference 2, Section 2. An M-channel multiplexed data acquisition system is shown in Figure 6.6. The multiplexer output drives a PGA whose gain can be adjusted on a per-channel basis depending on the channel signal level. This ensures that all channels utilize the full dynamic range of the ADC. The PGA gain is changed at the same time as the multiplexer is switched to a new channel. The ADC Convert Command is applied after the multiplexer and the PGA have settled to the required accuracy (1LSB). The maximum sampling frequency (when switching between channels) is limited by the multiplexer switching time tmux, the PGA settling time tpga, and the ADC conversion time tconv as shown in the formula
MULTIPLEXED DATA AQUISITION SYSTEM WITH PGA AND SAR ADC CONVERT COMMAND MUX PGA SAR ADC NO SHA) LPF a Example: M N- 12 and tconv *2Dsec, Then fin shAlin Figure 6.6 In a multiplexed system it is possible to have a positive fullscale signal on one channel and a negative fullscale signal on the other. When the multiplexer switches between these channels its output is a fullscale step voltage. All elements in the signal path must settle to the required accuracy(ILSB) before the conversion is made. The effect of inadequate settling is dc crosstalk between channels The SAR ADC chosen in this application has no internal sHa(similar to the industry-standard AD5 74-series), and therefore the input signal must be held constant (within 1LSB)during the conversion time in order to prevent encoding errors. This defines the maximum rate-of-change of the input signal: 1 LSB max conv The amplitude of a fullscale sinewave input signal is equal to(2 N)/2, or 2(N-1), and its maximum rate-of change is 2nf max -1 Ifmax 2 dt max Setting the two equations equal, and solving for fmax. π·2 t conv For example, if the ADC conversion time is 20usec(corresponding to a maximum sampling rate of slightly less than 50kSPS), and the resolution is 12-bits, then the
6 MULTIPLEXED DATA AQUISITION SYSTEM WITH PGA AND SAR ADC Figure 6.6 In a multiplexed system it is possible to have a positive fullscale signal on one channel and a negative fullscale signal on the other. When the multiplexer switches between these channels its output is a fullscale step voltage. All elements in the signal path must settle to the required accuracy (1LSB) before the conversion is made. The effect of inadequate settling is dc crosstalk between channels. The SAR ADC chosen in this application has no internal SHA (similar to the industry-standard AD574-series), and therefore the input signal must be held constant (within 1LSB) during the conversion time in order to prevent encoding errors. This defines the maximum rate-of-change of the input signal: dv dt LSB max t conv £ 1 The amplitude of a fullscale sinewave input signal is equal to (2^N)/2, or 2^(N-1), and its maximum rate-of change is dv dt max 2 f max 2 N 1 fmax 2 N = × - p = p × Setting the two equations equal, and solving for fmax, f N t conv max £ × 1 p 2 For example, if the ADC conversion time is 20µsec (corresponding to a maximum sampling rate of slightly less than 50kSPS), and the resolution is 12-bits, then the
maximum channel input signal frequency is limited to 4Hz. This may be adequate if the signals are dC, but the lack of a sha function severely limits the ability to process dynamic signals Adding a sha function to the adc as shown in Figure 6.7 allows processing of much faster signals with almost no increase in system complexity, since sampling adCs such as the AD1674 have the Sha function on-chip THE ADDITION OF A SHA FUNCTION TO THE ADC ALLOWS PROCESSING OF DYNAMIC INPUT SIGNALS PGA ADC CH M ■ n Gene Therefore, '. sias, then. 100ksPs Figure 6.7 TYPICAL TIMING DIAGRAM FOR MULTIPLEXED DATA ACQUISITION SYSTEM USING SHA SHA HOLD ACOUIREHOLD ADC CONVERT CONVERT VALD CHANGE CH GAN MUX PGA SETTLING Figure 6.8 The timing is adjusted such that the multiplexer and the Pga are switched immediately following the acquisition time of the SHA. If the combined multiplexer and Pga settling time is less than the AdC conversion time(see Figure 6.8), then the maximum sampling frequency of the system is given by
7 maximum channel input signal frequency is limited to 4Hz. This may be adequate if the signals are DC, but the lack of a SHA function severely limits the ability to process dynamic signals. Adding a SHA function to the ADC as shown in Figure 6.7 allows processing of much faster signals with almost no increase in system complexity, since sampling ADCs such as the AD1674 have the SHA function on-chip. THE ADDITION OF A SHA FUNCTION TO THE ADC ALLOWS PROCESSING OF DYNAMIC INPUT SIGNALS Figure 6.7 TYPICAL TIMING DIAGRAM FOR MULTIPLEXED DATA ACQUISITION SYSTEM USING SHA Figure 6.8 The timing is adjusted such that the multiplexer and the PGA are switched immediately following the acquisition time of the SHA. If the combined multiplexer and PGA settling time is less than the ADC conversion time (see Figure 6.8), then the maximum sampling frequency of the system is given by:
fs t acq +t conv sampling rate of 100kSPS is possible, if all the channels are addressed. The per d a The AD1674 has a conversion time of 9us, an acquisition time of lus to 12-bits channel sampling rate is obtained by dividing the adC sampling rate by m FILTERING CONSIDERATIONS IN DATA ACQUISITION SYSTEMS Filtering in data acquisition systems not only prevents aliasing of unwanted signals but also reduces noise by limiting bandwidth In a multiplexed system, there are basically two places to put filters: in each channel, and at the multiplexer output FILTERING IN A DATA ACQUISITION SYSTEM MUX PGA> LPF SHA CH M For Sequential Sampling, fe,< Figure 6.9 The filter at the input of each channel is used to prevent aliasing of signals which fall outside the Nyquist bandwidth. The per- channel sampling rate(assuming each channel is sampled at the same rate)is fs/M, and the corresponding Nyquist frequency is fs/2M. The filter should provide sufficient attenuation at f/2M to prevent dynamic range limitations due to aliasing. A second filter can be placed in the signal path between the multiplexer output and the adC, usually between the pga and the Sha. The cutoff frequency of this filter must be carefully chosen because of its impact on settling time. In a multiplexed system such as shown in Figure 6.7, there can be a fullscale step voltage change at the multiplexer output when it is switched between channels. This occurs if the signal on one channel is positive fullscale, and the signal on the adjacent channel is negative fullscale. From the timing diagram shown in Figure 6.8, the signal from the filter has essentially the entire conversion period (1/fs) to settle from the step voltage. The signal should settle to within ILSB of the final value in order not to introduce a significant error. The settling time requirement therefore places a lower limit on the filters cutoff frequency. The single- pole filter settling time required to maintain a given accuracy is shown in Figure 6.10. The settling time requirement is
8 fs t acq t conv £ + 1 The AD1674 has a conversion time of 9µs, an acquisition time of 1µs to 12-bits, and a sampling rate of 100kSPS is possible, if all the channels are addressed. The perchannel sampling rate is obtained by dividing the ADC sampling rate by M. FILTERING CONSIDERATIONS IN DATA ACQUISITION SYSTEMS Filtering in data acquisition systems not only prevents aliasing of unwanted signals but also reduces noise by limiting bandwidth. In a multiplexed system, there are basically two places to put filters: in each channel, and at the multiplexer output. FILTERING IN A DATA ACQUISITION SYSTEM Figure 6.9 The filter at the input of each channel is used to prevent aliasing of signals which fall outside the Nyquist bandwidth. The per-channel sampling rate (assuming each channel is sampled at the same rate) is fs /M, and the corresponding Nyquist frequency is fs /2M. The filter should provide sufficient attenuation at fs /2M to prevent dynamic range limitations due to aliasing. A second filter can be placed in the signal path between the multiplexer output and the ADC, usually between the PGA and the SHA. The cutoff frequency of this filter must be carefully chosen because of its impact on settling time. In a multiplexed system such as shown in Figure 6.7, there can be a fullscale step voltage change at the multiplexer output when it is switched between channels. This occurs if the signal on one channel is positive fullscale, and the signal on the adjacent channel is negative fullscale. From the timing diagram shown in Figure 6.8, the signal from the filter has essentially the entire conversion period (1/fs ) to settle from the step voltage. The signal should settle to within 1LSB of the final value in order not to introduce a significant error. The settling time requirement therefore places a lower limit on the filter's cutoff frequency. The single-pole filter settling time required to maintain a given accuracy is shown in Figure 6.10. The settling time requirement is
expressed in terms of the filter time constant and also the ratio of the filter cutoff frequency, fc,, to the ADC sampling frequency, fs SINGLE-POLE FILTER SETTLING TIME TO REQUIRED ACCURACY RESOLUTION, LSB (%FS) H OF TIME fe2/fs OF BITS CONSTANTS 1563 4.16 0.67 0.391 5.55 0.89 00977 6.9 1.11 0246802 0.0244 832132 970 0.00153 1.77 0.00038 12.48 2.00 0.000095 13.86 2.22 0.000024 15.25 Figure 6.10 As an example, assume that the adc is a 12-bit one sampling at 100kSPS. From the table in Figure 6.10, 8.32 time constants are required for the filter to settle to 12-bit accuracy, and ≥132,orfe2≥132kSPS While this filter will help prevent wideband noise from entering the SHA, it does not prouide the same function as the antialiasing filters at the input of each channel The above analysis assumes that the multiplexer/PGA combined settling time is significantly less than the filter settling time. If this is not the case, then the filter cutoff frequency must be larger, and in most cases it should be left out entirely in favor of per-channel filters SHA AND ADC SETTLING TIME REQUIREMENTS IN MULTIPLEXED APPLICATIONS We have discussed the importance of the fullscale settling time of the multiplexer/PGAfilter combination, but what is equally important is the ability of the adc to acquire the final value of the step voltage input signal to the required accuracy. Failure of any link in the signal chain to settle will result in dc crosstalk between adjacent channels and loss of accuracy If the data acquisition system uses a separate SHA and ADC, then the key specification to examine is the Sha acquisition time, which is usually specified as a the amount of time required to acquire a fullscale input signal to 0. 1% accuracy(10-bits)or.01% accuracy(13
9 expressed in terms of the filter time constant and also the ratio of the filter cutoff frequency, fc2,to the ADC sampling frequency, fs . SINGLE-POLE FILTER SETTLING TIME TO REQUIRED ACCURACY Figure 6.10 As an example, assume that the ADC is a 12-bit one sampling at 100kSPS. From the table in Figure 6.10, 8.32 time constants are required for the filter to settle to 12-bit accuracy, and fc fs 2 ³ 132 . , or fc2 ³ 132kSPS. While this filter will help prevent wideband noise from entering the SHA, it does not provide the same function as the antialiasing filters at the input of each channel. The above analysis assumes that the multiplexer/PGA combined settling time is significantly less than the filter settling time. If this is not the case, then the filter cutoff frequency must be larger, and in most cases it should be left out entirely in favor of per-channel filters. SHA AND ADC SETTLING TIME REQUIREMENTS IN MULTIPLEXED APPLICATIONS We have discussed the importance of the fullscale settling time of the multiplexer/PGA/filter combination, but what is equally important is the ability of the ADC to acquire the final value of the step voltage input signal to the required accuracy. Failure of any link in the signal chain to settle will result in dc crosstalk between adjacent channels and loss of accuracy. If the data acquisition system uses a separate SHA and ADC, then the key specification to examine is the SHA acquisition time, which is usually specified as a the amount of time required to acquire a fullscale input signal to 0.1% accuracy (10-bits) or 0.01% accuracy (13-
time is not specified for 0.01% accuracy or better, it should not be used in a 12-bif bits). In most cases, both 0. 1% and 0.01% times are specified If the SHa acquisition multiplexed application If the AdC is a sampling one(with internal SHa), the Sha acquisition time required to achieve a level of accuracy may still be specified as in the case of the AD1674(lus to 12-bit accuracy). SHA acquisition time and accuracy are not directly specified for some sampling ADCs, so the transient response specification should be examined. The transient response of the ADC (settling time to within 1 LSB for a fullscale step input)must be less the 1/fs, where fs is the ADC sampling rate. This often ignored specification may become the weakest link in the signal chain. In some cases neither the SHa acquisition time to specified accuracy nor the transient response specification may appear on the data sheet for the particular ADC, in which case it is probably not acceptable for multiplexed applications. Because of the difficulty in measuring and achieving better than 12-bit settling times using discrete components, the accuracy of most multiplexed data acquisition systems is limited to 12-bits Designing multiplexed systems with greater accuracy is extremely difficult, and using a single adc per channel should be strongly considered at higher resolutions SHA AND ADC CONSIDERATIONS IN MULTIPLEXED DATA ACQUISITION SYSTEMS Examine SHA Acquisition Time Specification to Required Accuracy: 0.1%=10bits 001%=13-bits If Sampling ADC, SHA Acquisition Time may not be given, so examine Transient Response Specification Inadequate Settling Results in Loss of Accuracy and causes DC Crosstalk Between Channels Multiplexing at greater than 12-bits Accuracy, or at Video Speeds is Extremely Difficult Figure 6.11 COMPLETE DATA ACQUISITION SYSTEMS ON A CHIP VLSI mixed-signal processing allows the integration of large and complex data acquisition circuits on a single chip. Most signal conditioning circuits including multiplexers, PGAs, and SHAs, may now be manufactured on the same chip as the ADC. This high level of integration permits data acquisition systems to be specified and tested as a single complex function. Such functionality relieves the designer of most of the burden of testing and calculating error budgets. The dC and ac characteristics of a complete data
1 0 bits). In most cases, both 0.1% and 0.01% times are specified. If the SHA acquisition time is not specified for 0.01% accuracy or better, it should not be used in a 12-bit multiplexed application. If the ADC is a sampling one (with internal SHA), the SHA acquisition time required to achieve a level of accuracy may still be specified, as in the case of the AD1674 (1µs to 12-bit accuracy). SHA acquisition time and accuracy are not directly specified for some sampling ADCs, so the transient response specification should be examined. The transient response of the ADC (settling time to within 1 LSB for a fullscale step input) must be less the 1/fs , where fs is the ADC sampling rate. This often ignored specification may become the weakest link in the signal chain. In some cases neither the SHA acquisition time to specified accuracy nor the transient response specification may appear on the data sheet for the particular ADC, in which case it is probably not acceptable for multiplexed applications. Because of the difficulty in measuring and achieving better than 12-bit settling times using discrete components, the accuracy of most multiplexed data acquisition systems is limited to 12-bits. Designing multiplexed systems with greater accuracy is extremely difficult, and using a single ADC per channel should be strongly considered at higher resolutions. SHA AND ADC CONSIDERATIONS IN MULTIPLEXED DATA ACQUISITION SYSTEMS Examine SHA Acquisition Time Specification to Required Accuracy: 0.1% = 10-bits 0.01% = 13-bits If Sampling ADC, SHA Acquisition Time may not be given, so examine Transient Response Specification Inadequate Settling Results in Loss of Accuracy and Causes DC Crosstalk Between Channels Multiplexing at greater than 12-bits Accuracy, or at Video Speeds is Extremely Difficult! Figure 6.11 COMPLETE DATA ACQUISITION SYSTEMS ON A CHIP VLSI mixed-signal processing allows the integration of large and complex data acquisition circuits on a single chip. Most signal conditioning circuits including multiplexers, PGAs, and SHAs, may now be manufactured on the same chip as the ADC. This high level of integration permits data acquisition systems to be specified and tested as a single complex function. Such functionality relieves the designer of most of the burden of testing and calculating error budgets. The DC and AC characteristics of a complete data
