SECTION 3 HIGH RESOLUTION SIGNAL CONDITIONING ADCS Sigma- Delta Adcs High Resolution, Low Frequency Measurement ADCs
1 SECTION 3 HIGH RESOLUTION SIGNAL CONDITIONING ADCs Sigma-Delta ADCs High Resolution, Low Frequency Measurement ADCs
section 3 HIGH RESOLUTION SIGNAL CONDITIONING ADCS Walt Kester, James Bryant, Joe Buxton The trend in ADCs and dACs is toward higher speeds and higher resolutions at reduced power levels. Modern data converters generally operate on + oV(dua single +3V supply This trend has created a number of design and app licationg supply)or +5V(single supply). There are now a few converters which operate or problems which were much less important in earlier data converters, where+15V supplies were the standard Lower supply voltages imply smaller input voltage ranges, and hence more susceptibility to noise from all potential sources: power supplies, references, digital signals, EMI/RFI, and probably most important, improper layout, grounding, and decoupling techniques. Single-supply adCs often have an input range which is not referenced to ground. Finding compatible single-supply drive amplifiers and dealing with level shifting of the input signal in direct-coupled applications also becomes a challenge In spite of these issues, components are now available which allow extremely high resolutions at low supply voltages and low power. This section discusses the applications problems associated with such components and shows techniques for successfully designing them into systems LOW POWER LOW VOLTAGE ADC DESIGN ISSUES Low Power ADCs ty pically run on #5V, +5V, +5/+3v, or+3v Lower Signal Swings Increase Sensitivity to All Types of Noise (Device, Power Supply, Logic, etc. Device Noise Increases at low quiescent currents Bandwidth Suffers as Supply Current Drops Input Common-Mode Range May be Limited Selection of Zero-Volt Input/output Amplifiers is Limited Auto-Calibration Modes Highly Desirable at High Resolutions Figure 3.1
2 SECTION 3 HIGH RESOLUTION SIGNAL CONDITIONING ADCs Walt Kester, James Bryant, Joe Buxton The trend in ADCs and DACs is toward higher speeds and higher resolutions at reduced power levels. Modern data converters generally operate on ±5V (dual supply) or +5V (single supply). There are now a few converters which operate on a single +3V supply. This trend has created a number of design and applications problems which were much less important in earlier data converters, where ±15V supplies were the standard. Lower supply voltages imply smaller input voltage ranges, and hence more susceptibility to noise from all potential sources: power supplies, references, digital signals, EMI/RFI, and probably most important, improper layout, grounding, and decoupling techniques. Single-supply ADCs often have an input range which is not referenced to ground. Finding compatible single-supply drive amplifiers and dealing with level shifting of the input signal in direct-coupled applications also becomes a challenge. In spite of these issues, components are now available which allow extremely high resolutions at low supply voltages and low power. This section discusses the applications problems associated with such components and shows techniques for successfully designing them into systems. LOW POWER, LOW VOLTAGE ADC DESIGN ISSUES Low Power ADCs typically run on 5V, +5V, +5/+3V, or +3V Lower Signal Swings Increase Sensitivity to All Types of Noise (Device, Power Supply, Logic, etc.) Device Noise Increases at Low Quiescent Currents Bandwidth Suffers as Supply Current Drops Input Common-Mode Range May be Limited Selection of Zero-Volt Input/Output Amplifiers is Limited Auto-Calibration Modes Highly Desirable at High Resolutions Figure 3.1
SIGMA-DELTA ADCS (CoURTESY OF JAMES M. BRYANT) Because Sigma-Delta is such an important and popular architecture for high resolution(16 to 24 bits) ADCs, the section begins with a basic description of this type of converter. Sigma-Delta Analog-Digital Converters have been known for nearly thirty years, but only recently has the technology(high-density digital vlsi existed to manufacture them as inexpensive monolithic integrated circuits. They are now used in many applications where a low-cost, low-bandwidth, low-power, high-resolution ADC is required There have been innumerable descriptions of the architecture and theory of sigma Delta ADCs but most commence with a maze of integrals and deteriorate from there. In the Applications Department at Analog Devices, we frequently encounter are convinced, from study of a typical published article, that it is too complex to o engineers who do not understand the theory of operation of Sigma-Delta ADCs comprehend easily There is nothing particularly difficult to understand about Sigma-Delta ADCs, as long as you avoid the detailed mathematics, and this section has been written in an attempt to clarify the subject. A Sigma-Delta ADC contains very simple analog electronics (a comparator, a switch, and one or more integrators and analo summing circuits), and quite complex digital computational circuitry. This circuitry consists of a digital signal processor DsP)which acts as a filter(generally, but not invariably, a low pass filter). It is not necessary to know precisely how the filter works to appreciate what it does To understand how a Sigma-Delta ADC works one should be familiar with the concepts of over-sampling, noise shaping, digital filtering and decimation S|GMA- DELTA②2-△ADcs Sigma-Delta ADCs are low-cost and have high resolution excellent DNL, low-power, although limited input bandwidth A∑△ ADC is simple The Mathematics, however is Complex This section Concentrates on What Actually Happens! Figure 3.2
3 SIGMA-DELTA ADCS (COURTESY OF JAMES M. BRYANT) Because Sigma-Delta is such an important and popular architecture for high resolution (16 to 24 bits) ADCs, the section begins with a basic description of this type of converter. Sigma-Delta Analog-Digital Converters have been known for nearly thirty years, but only recently has the technology (high-density digital VLSI) existed to manufacture them as inexpensive monolithic integrated circuits. They are now used in many applications where a low-cost, low-bandwidth, low-power, high-resolution ADC is required. There have been innumerable descriptions of the architecture and theory of SigmaDelta ADCs, but most commence with a maze of integrals and deteriorate from there. In the Applications Department at Analog Devices, we frequently encounter engineers who do not understand the theory of operation of Sigma-Delta ADCs and are convinced, from study of a typical published article, that it is too complex to comprehend easily. There is nothing particularly difficult to understand about Sigma-Delta ADCs, as long as you avoid the detailed mathematics, and this section has been written in an attempt to clarify the subject. A Sigma-Delta ADC contains very simple analog electronics (a comparator, a switch, and one or more integrators and analog summing circuits), and quite complex digital computational circuitry. This circuitry consists of a digital signal processor (DSP) which acts as a filter (generally, but not invariably, a low pass filter). It is not necessary to know precisely how the filter works to appreciate what it does. To understand how a Sigma-Delta ADC works one should be familiar with the concepts of over-sampling, noise shaping, digital filtering. and decimation. SIGMA-DELTA ( - ) ADCs Sigma-Delta ADCs are low-cost and have high resolution, excellent DNL, low-power, although limited input bandwidth A - ADC is Simple The Mathematics, however is Complex This section Concentrates on What Actually Happens! Figure 3.2
SIGMA-DELTA ADC KEY CONCEPTS Oversampling Noise Shaping Digital Filtering Decimation Figure 3.3 An AdC is a circuit whose digital output is proportional to the ratio of its analog input to its analog reference. Often, but by no means always, the scaling factor between the analog reference and the analog signal is unity, so the digital signal represents the normalized ratio of the two Figure 3. 4 shows the transfer characteristic of an ideal 3-bit unipolar ADC. The input to an AdC is analog and is not quantized, but its output is quantized. The transfer characteristic therefore consists of eight horizontal steps(when considering the offset, gain and linearity of an AdC we consider the line joining the midpoints of these steps) TRANSFER CHARACTERISTIC OF AN IDEAL 3-BIT UNIPOLAR ADC 111 110 SAME OUTPUT CODE DIGITAL 101- OUTPUT 010 I QUANTIZATION ERR=±12LsB ←十 001 ANALOG INPUT Figure 3.4 Digital full scale(all"1"s)corresponds to 1 LSB below the analog full scale(the reference or some multiple thereof). This is because, as mentioned above the digital code represents the normalized ratio of the analog signal to the reference, and if this were unity, the digital code would be all O"s and"1"in the bit aboue the msb
4 SIGMA-DELTA ADC KEY CONCEPTS Oversampling Noise Shaping Digital Filtering Decimation Figure 3.3 An ADC is a circuit whose digital output is proportional to the ratio of its analog input to its analog reference. Often, but by no means always, the scaling factor between the analog reference and the analog signal is unity, so the digital signal represents the normalized ratio of the two. Figure 3.4 shows the transfer characteristic of an ideal 3-bit unipolar ADC. The input to an ADC is analog and is not quantized, but its output is quantized. The transfer characteristic therefore consists of eight horizontal steps (when considering the offset, gain and linearity of an ADC we consider the line joining the midpoints of these steps). TRANSFER CHARACTERISTIC OF AN IDEAL 3-BIT UNIPOLAR ADC Figure 3.4 Digital full scale (all "1"s) corresponds to 1 LSB below the analog full scale (the reference or some multiple thereof). This is because, as mentioned above, the digital code represents the normalized ratio of the analog signal to the reference, and if this were unity, the digital code would be all "0"s and "1" in the bit above the MSB
The (ideal) ADC transitions take place at_lsB above zero and thereafter every LSB, until 1_ LSB below analog full scale. Since the analog input to an adC can take any value, but the digital output is quantized, there may be a difference of up to LSB between the actual analog input and the exact value of the digital output This is known as the quantization error or quantization uncertainty. In AC (sampling)applications, this quantization error gives rise to quantization noise. If we apply a fixed input to an ideal AdC, we will always obtain the same output, and the resolution will be limited by the quantization error. Suppose, however, that we add some ac (dither)to the fixed signal, take a large number of samples, and prepare a histogram of the results. We will obtain something like the result in Figure 3. 5. If we calculate the mean value of a large number of samples, we will find that we can measure the fixed signal with greater resolution than that of the AdC we are using This procedure is known as oUer-sampling. OVERSAMPLING WITH DITHER ADDED TO INPUT N AND N.1 Figure 3.5 The AC(dither) that we add may be a sine-wave, a tri-wave, or Gaussian noise(but not a square wave) and, with some types of sampling AdCs(including Sigma-Delta ADCs), an external dither signal is unnecessary, since the adC generates its own Analysis of the effects of differing dither waveforms and amplitudes is complex and for the purposes of this section, unnecessary. what we do need to know is that with the simple over-sampling described here, the number of samples must be doubled for each bit of increase in effective resolutio If, instead of a fixed DC signal, the signal that we are over-sampling is an ac signal then it is not necessary to add a dither signal to it in order to over-sample, since the signal is moving anyway (If the ac signal is a single tone harmonically related to the sampling frequency, dither may be necessary, but this is a special case.) Let us consider the technique of over-sampling with an analysis in the frequency domain. Where a dC conversion has a quantization error of up to_LSB, a sampled data system has quantization noise. As we have already seen, a perfect classica
5 The (ideal) ADC transitions take place at _ LSB above zero and thereafter every LSB, until 1_ LSB below analog full scale. Since the analog input to an ADC can take any value, but the digital output is quantized, there may be a difference of up to _ LSB between the actual analog input and the exact value of the digital output. This is known as the quantization error or quantization uncertainty. In AC (sampling) applications, this quantization error gives rise to quantization noise. If we apply a fixed input to an ideal ADC, we will always obtain the same output, and the resolution will be limited by the quantization error. Suppose, however, that we add some AC (dither) to the fixed signal, take a large number of samples, and prepare a histogram of the results. We will obtain something like the result in Figure 3.5. If we calculate the mean value of a large number of samples, we will find that we can measure the fixed signal with greater resolution than that of the ADC we are using. This procedure is known as over-sampling. OVERSAMPLING WITH DITHER ADDED TO INPUT Figure 3.5 The AC (dither) that we add may be a sine-wave, a tri-wave, or Gaussian noise (but not a square wave) and, with some types of sampling ADCs (including Sigma-Delta ADCs), an external dither signal is unnecessary, since the ADC generates its own. Analysis of the effects of differing dither waveforms and amplitudes is complex and, for the purposes of this section, unnecessary. What we do need to know is that with the simple over-sampling described here, the number of samples must be doubled for each _bit of increase in effective resolution. If, instead of a fixed DC signal, the signal that we are over-sampling is an AC signal, then it is not necessary to add a dither signal to it in order to over-sample, since the signal is moving anyway. (If the AC signal is a single tone harmonically related to the sampling frequency, dither may be necessary, but this is a special case.) Let us consider the technique of over-sampling with an analysis in the frequency domain. Where a DC conversion has a quantization error of up to _ LSB, a sampled data system has quantization noise. As we have already seen, a perfect classical
N-bit sampling AdC has an rms quantization noise of q/(sgrt 12)uniformly distributed within the Nyquist band of dC to fs/2(where q is the value of an lsB and fs is the sampling rate). Therefore, its SNR with a full-scale sinewave input will be(6.02N+ 1.76)dB. If the adC is less than perfect, and its noise is greater than its theoretical minimum quantization noise then its effective resolution will be less than N-bits. Its actual resolution(often known as its Effective Number of bits or ENOB)will be defined by ENOB= SNR-176dB 6.02dB SAMPLING ADC QUANTIZATION NOISE OUTPUT SIGNAL ADC RMS QUANTIZATION NOISE =gN 12 Figure 3.6 If we choose a much higher sampling rate the quantization noise is distributed over a wider bandwidth as shown in Figure 3.7. If we then apply a digital low pass filter LPF) to the output, we remove much of the quantization noise but do not affect the wanted signal- so the ENOB is improved. We have accomplished a high resolution A/d conversion with a low resolution ADC
6 N-bit sampling ADC has an rms quantization noise of q/(sqrt 12) uniformly distributed within the Nyquist band of DC to fs /2 (where q is the value of an LSB and fs is the sampling rate). Therefore, its SNR with a full-scale sinewave input will be (6.02N + 1.76) dB. If the ADC is less than perfect, and its noise is greater than its theoretical minimum quantization noise, then its effective resolution will be less than N -bits. Its ac tu al r eso lutio n ( o fte nk n o wnas its E f fe c tiv eNu m bero f B its or E N OB )will bede f ine d by ENOB SNR dB dB = - 176 6 02 . . . SAMPLING ADC QUANTIZATION NOISE Figure 3.6 If we choose a much higher sampling rate, the quantization noise is distributed over a wider bandwidth as shown in Figure 3.7. If we then apply a digital low pass filter (LPF) to the output, we remove much of the quantization noise, but do not affect the wanted signal - so the ENOB is improved. We have accomplished a high resolution A/D conversion with a low resolution ADC
OVERSAMPLING FOLLOWED BY DIGITAL FILTERING AND DECIMATION IMPROVES SNR AND ENOB fs ADC DECIMATOR QUANTIZATION NOISI REMOVED BY DIGITAL FILTER Figure 3.7 Since the bandwidth is reduced by the digital output filter, the output data rate may be lower than the original sampling rate and still satisfy the Nyquist criterion. This may be achieved by passing every Mth result to the output and discarding the remainder. The process is known as"decimation"by a factor of M. Despite the origins of the term(decem is Latin for ten), M can have any integer value, provided that the output data rate is more than twice the signal bandwidth. Decimation does not cause any loss of information(see Figure 3.8) DECIMATION AFTER SAMPLING AT fs AND FILTERING, THE OUTPUT DATA RATE MAY BE REDUCED TO f/M WITHOUT LOSS OF INFORMATION FILTER PASSBAND 2 Figure 3.8
7 OVERSAMPLING FOLLOWED BY DIGITAL FILTERING AND DECIMATION IMPROVES SNR AND ENOB Figure 3.7 Since the bandwidth is reduced by the digital output filter, the output data rate may be lower than the original sampling rate and still satisfy the Nyquist criterion. This may be achieved by passing every Mth result to the output and discarding the remainder. The process is known as "decimation" by a factor of M. Despite the origins of the term (decem is Latin for ten), M can have any integer value, provided that the output data rate is more than twice the signal bandwidth. Decimation does not cause any loss of information (see Figure 3.8). DECIMATION Figure 3.8
If we simply use over-sampling to improve resolution, we must over-sample by a factor of 2 2N to obtain an N-bit increase in resolution. The Sigma-Delta converte does not need such a high over-sampling ratio because it not only limits the signal passband, but also shapes the quantization noise so that most of it falls outside this passband If we take a l-bit adc (generally known as a comparator), drive it with the output of an integrator, and feed the integrator with an input signal summed with the output of a 1-bit DAC fed from the ADC output, we have a first-order Sigma-Delta modulator as shown in Figure 3.9. Add a digital low pass filter (LPF)and decimator at the digital output, and we have a Sigma-Delta ADC: the Sigma-Delta modulator shapes the quantization noise so that it lies above the passband of the digital output filter, and the eNob is therefore much larger than would otherwise be expected from the over-sampling ratio FIRST ORDER SIGMA-DELTA ADC 当∑ VREF Figure 3.9 B than one integration and summing stas Delta modulator, we can achieve higher orders of quantization noise shaping and even better ENOB for a given over-sampling ratio as is shown in figure 3. 10 for both a first and second-order Sigma-Delta modulator The block diagram for the second order Sigma-Delta modulator is shown in Figure 3. 11. Third, and higher, order Sigma- Delta ADCs were once thought to be potentially unstable at some values of input- recent analyses using finite rather than infinite gains in the comparator have shown that this is not necessarily so, but even if instability does start to occur, it is not important, since the DSP in the digital filter and decimator can be made to recognize incipient instability and react to prevent it
8 If we simply use over-sampling to improve resolution, we must over-sample by a factor of 2^2N to obtain an N-bit increase in resolution. The Sigma-Delta converter does not need such a high over-sampling ratio because it not only limits the signal passband, but also shapes the quantization noise so that most of it falls outside this passband. If we take a 1-bit ADC (generally known as a comparator), drive it with the output of an integrator, and feed the integrator with an input signal summed with the output of a 1-bit DAC fed from the ADC output, we have a first-order Sigma-Delta modulator as shown in Figure 3.9. Add a digital low pass filter (LPF) and decimator at the digital output, and we have a Sigma-Delta ADC: the Sigma-Delta modulator shapes the quantization noise so that it lies above the passband of the digital output filter, and the ENOB is therefore much larger than would otherwise be expected from the over-sampling ratio. FIRST ORDER SIGMA-DELTA ADC Figure 3.9 By using more than one integration and summing stage in the Sigma-Delta modulator, we can achieve higher orders of quantization noise shaping and even better ENOB for a given over-sampling ratio as is shown in Figure 3.10 for both a first and second-order Sigma-Delta modulator. The block diagram for the secondorder Sigma-Delta modulator is shown in Figure 3.11. Third, and higher, order Sigma-Delta ADCs were once thought to be potentially unstable at some values of input - recent analyses using finite rather than infinite gains in the comparator have shown that this is not necessarily so, but even if instability does start to occur, it is not important, since the DSP in the digital filter and decimator can be made to recognize incipient instability and react to prevent it
SIGMA-DELTA MODULATORS SHAPE QUANTIZATION NOISE DIGITAl 一 FILTER igure 3. 10 SECOND-ORDER SIGMA-DELTA ADC ))1 Figure 3.11 and the amount of over-sampling necessary to achieve a particular SNR odulator Figure 3.12 shows the relationship between the order of the Sigma-Delta
9 SIGMA-DELTA MODULATORS SHAPE QUANTIZATION NOISE Figure 3.10 SECOND-ORDER SIGMA-DELTA ADC Figure 3.11 Figure 3.12 shows the relationship between the order of the Sigma-Delta modulator and the amount of over-sampling necessary to achieve a particular SNR
SNR VERSUS OVERSAMPLING RATIO FOR FIRST. SECOND, AND THIRD-ORDER LOOPS 120 THIRD-ORDER LOOP. SNR dB) 15dB OCTAVE FIRST-ORDER LOOP 2nd ORDER LOOPS DO NOT OBEY LINEAR MODEL OVERSAMPLING RATIO, K Figure 3. 12 The Sigma-Delta ADCs that we have described so far contain integrators, which are low pass filters, whose passband extends from DC. Thus, their quantization noise is pushed up in frequency. At present, all commercially available Sigma-Delta ADCs are of this type(although some which are intended for use in audio or telecommunications applications contain bandpass rather than lowpass digital filters to eliminate any system dC offsets). Sigma-Delta DCs are available with resolutions up to 24-bits for DC measurement applications(AD7710, AD7711 AD7712, AD7713, AD7714), and with resolutions of 18-bits for high quality digita audio applications(AD1879) But there is no particular reason why the filters of the Sigma-Delta modulator should be LPFs, except that traditionally adCs have been thought of as being baseband devices, and that integrators are somewhat easier to construct than bandpass filters. If we replace the integrators in a Sigma-Delta ADC with bandpass filters(BPFs), the quantization noise is moved up and down in frequency to leave a virtually noise-free region in the pass-band(see Reference 1). If the digital filter is then programmed to have its pass band in this region, we have a Sigma-Delta ADC with a bandpass, rather than a low pass characteristic(see Figure 3. 13). Although studies of this architecture are in their infancy, such ADCs would seem to be ideally suited for use in digital radio receivers, medical ultrasound, and a number of other application
1 0 SNR VERSUS OVERSAMPLING RATIO FOR FIRST, SECOND, AND THIRD-ORDER LOOPS Figure 3.12 The Sigma-Delta ADCs that we have described so far contain integrators, which are low pass filters, whose passband extends from DC. Thus, their quantization noise is pushed up in frequency. At present, all commercially available Sigma-Delta ADCs are of this type (although some which are intended for use in audio or telecommunications applications contain bandpass rather than lowpass digital filters to eliminate any system DC offsets). Sigma-Delta ADCs are available with resolutions up to 24-bits for DC measurement applications (AD7710, AD7711, AD7712, AD7713, AD7714), and with resolutions of 18-bits for high quality digital audio applications (AD1879). But there is no particular reason why the filters of the Sigma-Delta modulator should be LPFs, except that traditionally ADCs have been thought of as being baseband devices, and that integrators are somewhat easier to construct than bandpass filters. If we replace the integrators in a Sigma-Delta ADC with bandpass filters (BPFs), the quantization noise is moved up and down in frequency to leave a virtually noise-free region in the pass-band (see Reference 1). If the digital filter is then programmed to have its pass-band in this region, we have a Sigma-Delta ADC with a bandpass, rather than a low pass characteristic (see Figure 3.13). Although studies of this architecture are in their infancy, such ADCs would seem to be ideally suited for use in digital radio receivers, medical ultrasound, and a number of other applications