《模拟电路设计》（英文版）SECTION 2 HIGH SPEED OP AMPS.pdf_大学文库

sectioN 2 HIGH SPEED OP AMPS Walt Jung and walt Kester Modern system design increasingly makes use of high speed ICs as circuit building blocks. With bandwidths going up and up, demands are placed on the designer for faster and more power efficient circuits. The default high speed amplifier has changed over the years, with high speed complementary bipolar(CB) process ICs such as the A846 and AD847 in use just about ten years at this writing durin this time the general utility/availability of these and other iCs have raised the " high speed" common performance denominator to 50MHz. The most recent extended AD8001/AD8002, the AD9631/9632 and the Ad8036/AD8037 now extend the the frequency complementary bipolar (XFCB) process high speed devices such as operating range into the UhF region. Of course, a traditional performance barrier has been speed, or perhaps more accurately, painless speed. While fast IC amplifiers have been around for some time until more recently they simply havent been the easiest to use. As an example, devices with substantial speed increases over 741/301A era types, namely the 318- family, did so at the expense of relatively poor settling and capacitive loading characteristics. Modern CB process parts like the AD84X series provide far greater speed, faster settling, and do so at low user cost. Still, the application of high performance fast amplifiers is never entirely a cookbook process, so designers still need to be wary of many inter-related key issues. This includes not just the amplifier selection, but also control of parasitics and other potentially performance-limiting details in the surrounding circuit It is worth underscoring that reasons for the"speed revolution"lie not just in affordability of the new high speed ICs, but is also rooted in their ease of use. Compared to earlier high speed ICs, CB process devices are generally more stable with capacitive loads(with higher phase margins in general), have lower DC errors consume less power for a given speed, and are all around more"user friendly ". Taking this a step further, XFCB family devices, which extend the utility of the op amp to literally hundreds of MHz, are understandably less straightforward in terms of their application(as is any amplifier operating over such a range). Thus, getting the most from these modern devices definitely stresses the total environment aspects of design Another major ease of use feature found in today's linear ICs is a much wider range of supply voltage characterization. While the older +15V standard is still much in use, there is a trend towards including more performance data at popular lower voltages, such as +5V, or+5V only, single supply operation. The most recent devices using the lower voltage XFCB process use supply voltages of either +5V, or simply +5V only. The trend towards lower supply voltages is unmistakable, with a goal of squeezing the highest performance from a given voltage/power circuit environment These"ease of use"design aspects with current ICs are illustrated in this chapter

2 SECTION 2 HIGH SPEED OP AMPS Walt Jung and Walt Kester Modern system design increasingly makes use of high speed ICs as circuit building blocks. With bandwidths going up and up, demands are placed on the designer for faster and more power efficient circuits. The default high speed amplifier has changed over the years, with high speed complementary bipolar (CB) process ICs such as the AD846 and AD847 in use just about ten years at this writing. During this time, the general utility/availability of these and other ICs have raised the “high speed” common performance denominator to 50MHz. The most recent extended frequency complementary bipolar (XFCB) process high speed devices such as the AD8001/AD8002, the AD9631/9632 and the AD8036/AD8037 now extend the operating range into the UHF region. Of course, a traditional performance barrier has been speed, or perhaps more accurately, painless speed. While fast IC amplifiers have been around for some time, until more recently they simply haven’t been the easiest to use. As an example, devices with substantial speed increases over 741/301A era types, namely the 318- family, did so at the expense of relatively poor settling and capacitive loading characteristics. Modern CB process parts like the AD84X series provide far greater speed, faster settling, and do so at low user cost. Still, the application of high performance fast amplifiers is never entirely a cookbook process, so designers still need to be wary of many inter-related key issues. This includes not just the amplifier selection, but also control of parasitics and other potentially performance-limiting details in the surrounding circuit. It is worth underscoring that reasons for the "speed revolution" lie not just in affordability of the new high speed ICs, but is also rooted in their ease of use. Compared to earlier high speed ICs, CB process devices are generally more stable with capacitive loads (with higher phase margins in general), have lower DC errors, consume less power for a given speed, and are all around more "user friendly". Taking this a step further, XFCB family devices, which extend the utility of the op amp to literally hundreds of MHz, are understandably less straightforward in terms of their application (as is any amplifier operating over such a range). Thus, getting the most from these modern devices definitely stresses the “total environment” aspects of design. Another major ease of use feature found in today's linear ICs is a much wider range of supply voltage characterization. While the older ±15V standard is still much in use, there is a trend towards including more performance data at popular lower voltages, such as ±5V, or +5V only, single supply operation. The most recent devices using the lower voltage XFCB process use supply voltages of either ±5V, or simply +5V only. The trend towards lower supply voltages is unmistakable, with a goal of squeezing the highest performance from a given voltage/power circuit environment. These "ease of use" design aspects with current ICs are illustrated in this chapter

along with parasitic issues, optimizing performance over supply ranges, and low distortion stages in a variety of applications. DRIVING CAPACITIVE LOADS From system and signal fidelity points of view, transmission line coupling between k tages is best, and is described in some detail in the next section. However, complete ransmission line system design may not always be possible or practical. In addition, various other parasitic issues need careful consideration in high performance designs. One such problem parasitic is amplifier load capacitance, which potentially comes into play for all wide bandwidth situations which do not use transmission line signal coupling a general design rule for wideband linear drivers is that capacitive loading(cap loading)effects should always be considered. This is because PC board capacitance can build up quickly, especially for wide and long signal runs over ground planes insulated by thin, higher k dielectric. For example, a 0.025" Pc trace using a G-10 dielectric of 0.03"over a ground plane will run about 22p F/foot(Reference 1). Even relatively small load capacitance (i.e, <100 pF) can be troublesome, since while not causing outright oscillation, it can still stretch amplifier settling time to greater than desirable levels for a given accuracy The effects of cap loading on high speed amplifier outputs are not simply detrimental, they are actually an anathema to high quality signals. However, before- the -fact designer know ledge still allows high circuit performance, by employing various tricks of the trade to combat the capacitive loading. If it is not driven via a transmission line, remote signal circuitry should be checked for capacitive loading very carefully, and characterized as best possible. Drivers which face poorly defined load capacitance should be bullet-proofed accordingly with an appropriate design technique from the options list below Short of a true matched transmission line system, a number of ways exist to drive a load which is capacitive in nature while maintaining amplifier stability. Custom capacitive load (cap load) compensation, includes two possible options, namely a); overcompensation, and b); an intentionally forced-high loop noise gain allowing crossover in a stable region. Both of these steps can be effective in special situations, as they reduce the amplifier's effective closed loop bandwidth, so as to restore stability in the presence of cap loading Overcompensation of the amplifier, when possible, reduces amplifier bandwidth so that the additional load capacitance no longer represents a danger to phase margin. As a practical matter however, amplifier compensation nodes to allow this are available on few high speed amplifiers. One such useful example is the AD829 compensated by a single capacitor at pin 5. In general, almost any amplifier using sternal compensation can always be over compensated to reduce bandwidth. This will restore stability against cap loads, by lowering the amplifiers unity gain frequency

3 along with parasitic issues, optimizing performance over supply ranges, and low distortion stages in a variety of applications. DRIVING CAPACITIVE LOADS From system and signal fidelity points of view, transmission line coupling between stages is best, and is described in some detail in the next section. However, complete transmission line system design may not always be possible or practical. In addition, various other parasitic issues need careful consideration in high performance designs. One such problem parasitic is amplifier load capacitance, which potentially comes into play for all wide bandwidth situations which do not use transmission line signal coupling. A general design rule for wideband linear drivers is that capacitive loading (cap loading) effects should always be considered. This is because PC board capacitance can build up quickly, especially for wide and long signal runs over ground planes insulated by thin, higher K dielectric. For example, a 0.025” PC trace using a G-10 dielectric of 0.03” over a ground plane will run about 22pF/foot (Reference 1). Even relatively small load capacitance (i.e., <100 pF) can be troublesome, since while not causing outright oscillation, it can still stretch amplifier settling time to greater than desirable levels for a given accuracy. The effects of cap loading on high speed amplifier outputs are not simply detrimental, they are actually an anathema to high quality signals. However, beforethe-fact designer knowledge still allows high circuit performance, by employing various tricks of the trade to combat the capacitive loading. If it is not driven via a transmission line, remote signal circuitry should be checked for capacitive loading very carefully, and characterized as best possible. Drivers which face poorly defined load capacitance should be bullet-proofed accordingly with an appropriate design technique from the options list below. Short of a true matched transmission line system, a number of ways exist to drive a load which is capacitive in nature while maintaining amplifier stability. Custom capacitive load (cap load) compensation, includes two possible options, namely a); overcompensation, and b); an intentionally forced-high loop noise gain allowing crossover in a stable region. Both of these steps can be effective in special situations, as they reduce the amplifier’s effective closed loop bandwidth, so as to restore stability in the presence of cap loading. Overcompensation of the amplifier, when possible, reduces amplifier bandwidth so that the additional load capacitance no longer represents a danger to phase margin. As a practical matter however, amplifier compensation nodes to allow this are available on few high speed amplifiers. One such useful example is the AD829, compensated by a single capacitor at pin 5. In general, almost any amplifier using external compensation can always be over compensated to reduce bandwidth. This will restore stability against cap loads, by lowering the amplifier’s unity gain frequency

Drawbacks of this approach are the loss of bandwidth as Rx works against Cl, the loss of voltage swing, a possible lower slew rate limit due to IMAX and Cl, and a gain error due to the Rx- RL division. The gain error can be optionally compensated with riN, which is ratioed to RF as Rl is to Rx. In this example, a+100mA output from the op amp into CLcan slew VouT at a rate of 100V/us, far below the intrinsic AD811 slew rate of 2500V/us. Although the drawbacks are serious, this form of cap load compensation is nevertheless useful because of its simplicity. If the amplifier not otherwise protected, then an Rx resistor of 50-100ohms should be used with virtually any amplifier facing capacitive loading. Although a non-inverting amplifier is shown, the technique is equally applicable to inverter stages With very speed high amplifiers, or in applications where lowest settling time is critical, even small values of load capacitance can be disruptive to frequency response, but are nevertheless sometimes inescapable. One case in point is an amplifier used for driving ADC inputs Since high speed ADC inputs quite often look capacitive in nature, this presents an oil/water type problem. In such cases the amplifier must be stable driving the capacitance, but it must also preserve its best bandwidth and settling time characteristics. To address this type of cap load case performance, Rs and Cl data for a specified settling time is most appropriate Some applications, in particular those that require driving the relatively high impedance of an ADC, do not have a convenient back termination resistor to dampen the effects of capacitive loading. At high frequencies, an amplifiers output impedance is rising with frequency and acts like an inductance, which in combination with Cl causes peaking or even worse, oscillation When the bandwidth of an amplifier is an appreciable percentage of device ft the situation is complicated by the fact that the loading effects are reflected back into its internal stages. In spite of this, the basic behavior of most very wide bandwidth amplifiers such as the AD8001 is very simila In general, a small damping resistor(Rs) placed in series with Cl will help restore the desired response(see Figure 2.4). The best choice for this resistors value will depend upon the criterion used in determining the desired response. Traditionally simply stability or an acceptable amount of peaking has been used, but a more strict measure such as0. 1%(or even 0.01%)settling will yield different values For a given amplifier, a family of rs-CL curves exists, such as those of Figure 2.4. These data will aid in selecting Rs for a given application

6 Drawbacks of this approach are the loss of bandwidth as RX works against CL, the loss of voltage swing, a possible lower slew rate limit due to IMAX and CL, and a gain error due to the RX-RL division. The gain error can be optionally compensated with RIN, which is ratioed to RF as RL is to RX. In this example, a ±100mA output from the op amp into CLcan slew VOUT at a rate of 100V/µs, far below the intrinsic AD811 slew rate of 2500V/µs. Although the drawbacks are serious, this form of cap load compensation is nevertheless useful because of its simplicity. If the amplifier is not otherwise protected, then an RX resistor of 50-100ohms should be used with virtually any amplifier facing capacitive loading. Although a non-inverting amplifier is shown, the technique is equally applicable to inverter stages. With very speed high amplifiers, or in applications where lowest settling time is critical, even small values of load capacitance can be disruptive to frequency response, but are nevertheless sometimes inescapable. One case in point is an amplifier used for driving ADC inputs. Since high speed ADC inputs quite often look capacitive in nature, this presents an oil/water type problem. In such cases the amplifier must be stable driving the capacitance, but it must also preserve its best bandwidth and settling time characteristics. To address this type of cap load case performance, Rs and CL data for a specified settling time is most appropriate. Some applications, in particular those that require driving the relatively high impedance of an ADC, do not have a convenient back termination resistor to dampen the effects of capacitive loading. At high frequencies, an amplifier’s output impedance is rising with frequency and acts like an inductance, which in combination with CL causes peaking or even worse, oscillation. When the bandwidth of an amplifier is an appreciable percentage of device ft ,the situation is complicated by the fact that the loading effects are reflected back into its internal stages. In spite of this, the basic behavior of most very wide bandwidth amplifiers such as the AD8001 is very similar. In general, a small damping resistor (Rs ) placed in series with CL will help restore the desired response (see Figure 2.4). The best choice for this resistor’s value will depend upon the criterion used in determining the desired response. Traditionally, simply stability or an acceptable amount of peaking has been used, but a more strict measure such as 0.1% (or even 0.01%) settling will yield different values. For a given amplifier, a family of Rs - CLcurves exists, such as those of Figure 2.4. These data will aid in selecting Rs for a given application

AD8001 Rs REQIRED FOR VARIOUS CL VALUES G#+2 0.1% SETTLING G=+2 20 OVERSHOOT CL (PF) Figure 2.4 The basic shape of this curve can be easily explained. When Cl is very small,no resistor is necessary. When Cl increases to some threshold value an Rs becomes necessary. Since the frequency at which the damping is required is related to the Rs CL time constant, the Rs needed will initially increase rapidly from zero, and then will decrease as Cl is increased further A relatively strict requirement, such as for 0. 1%, settling will generally require a larger Rs for a given Cl, giving a curve falling higher (in terms of rs) than that for a less stringent requirement, such as 20%overshoot. For the common gain condition of +2, these two curves are plotted in the figure for 0. 1% settling(upper-most curve)and 20% overshoot(middle curve).It is also worth mentioning that higher closed loop gains lessen the problem dramatically, and will require less Rs for the same performance. The third (lower- most)curve illustrates this, demonstrating a closed loop gain of 10 Rs requirement for 20% overshoot for the AD8001 amplifier. This can be related to the earlier discussion associated with Figure 2.2 The recommended values for Rs will optimize response, but it is important to note that generally Cl will degrade the maximum bandwidth and settling time performance which is achievable In the limit, a large Rs Cl time constant will dominate the response. In any given application, the value for Rs should be taken as a starting point in an optimization process which accounts for board parasitics and other secondary effects Active or "in-the-Loop "cap load compensation can also be used as shown in Figure 2.5, and this scheme modifies the passive configuration to prouide feedback correcti for the dc low frequency gain error associated with Rx. In contrast to the passive form, active compensation can only be used with voltage feedback amplifiers, because current feedback amplifiers don t allow the integrating connection of Cl

7 AD8001 RS REQIRED FOR VARIOUS CL VALUES Figure 2.4 The basic shape of this curve can be easily explained. When CLis very small, no resistor is necessary. When CLincreases to some threshold value an Rs becomes necessary. Since the frequency at which the damping is required is related to the Rs•CLtime constant, the Rs needed will initially increase rapidly from zero, and then will decrease as CLis increased further. A relatively strict requirement, such as for 0.1%, settling will generally require a larger Rs for a given CL, giving a curve falling higher (in terms of Rs ) than that for a less stringent requirement, such as 20% overshoot. For the common gain condition of +2, these two curves are plotted in the figure for 0.1% settling (upper-most curve) and 20% overshoot (middle curve). It is also worth mentioning that higher closed loop gains lessen the problem dramatically, and will require less Rs for the same performance. The third (lowermost) curve illustrates this, demonstrating a closed loop gain of 10 Rs requirement for 20% overshoot for the AD8001 amplifier. This can be related to the earlier discussion associated with Figure 2.2. The recommended values for Rs will optimize response, but it is important to note that generally CLwill degrade the maximum bandwidth and settling time performance which is achievable. In the limit, a large Rs•CLtime constant will dominate the response. In any given application, the value for Rs should be taken as a starting point in an optimization process which accounts for board parasitics and other secondary effects. Active or “in-the-loop” cap load compensation can also be used as shown in Figure 2.5, and this scheme modifies the passive configuration to provide feedback correction for the DC & low frequency gain error associated with RX. In contrast to the passive form, active compensation can only be used with voltage feedback amplifiers, because current feedback amplifiers don’t allow the integrating connection of CF

feedback hookup, as well as size of the external cap loading. In other words, it can be transparent to the user in the sense that no specific design conditions need be set to make it work(other than selecting an ic which employs it). Some amplifiers using internal cap load compensation are the AD8 47 and the AD817, and their dual equivalents, AD827 and AD826 There are, however, some caveats also associated with this internal compensation scheme. As with the passive compensation techniques, bandwidth decreases as the device slows down to prevent oscillation with higher load currents. Also, this adaptive compensation network has its greatest effect when enough output current flows to produce significant voltage drop across the CF network. Conversely, at small signal levels, the effect of the network on speed is less, so greater ringing may actually be possible for some circuits for lower-level outputs. RESPONSE OF INTERNAL CAP LOAD COMPENSATED AMPLIFIER VARIES WITH SIGNAL LEVEL (A) VOUT = 10V p-p (B)VOUT 200mv p-p Vertical Scale: 5V/div Vertical Scale, 100m Vldiv ■■■ ■■■■■ ■■■■■ ■■■■■■■ ■■■■■■ ■□- □〓i Horizontal Scale: 500ns/div AD817 INVERTER RF ERIN = 1kQ2 RL= lkQ2, CL= InF, Vs =t15V Figure 2.7 The dynamic nature of this internal cap load compensation is illustrated in Figure 2.7, which shows an AD8 17 unity gain inverter being exercised at both high and low output levels, with common conditions of Vs=+15V, Rl= 1kohm, CL= InF, and using 1kohm input/feedback resistors. In both photos the input signal is on the top trace and the output signal is on the bottom trace, and the time scale is fixed. In the 10Vp-p output(A) photo at the left, the output has slowed down appreciably to accommodate the capacitive load, but settling is still relatively clean, with a small percentage of overshoot. This indicates that for this high level case, the bandwidth reduction due to CL is most effective. However, in the(B) photo at the right, the 200mVp-p output shows greater overshoot and ringing, for the lower level signal The point is made that, to some degree at least, the relative cap load immunity of this type of internally cap load compensated amplifier is signal dependent