Cache miss:阻塞式(blocking,stall多个周期 2 Imm16 E ALU result 32 32 I-Cache Rs BusA 0123 inon7 D-Cache RA Instruction Rt 5 Address RB BusB 32 Address Data_out 1 RW BusW 23 Data_in 32 32 01 Rd clk I-Cache miss or D-Cache miss causes pipeline to stall Interface to L2 Cache or Main MemoryCache miss：阻塞式（blocking，stall多个周期？)