requirement, you will generally require an ADC having a much higher sampling rat than is actua lly needed Figure 5. 12 shows the approximate SFDR versus input frequency for the series of low distortion ADCs. Notice that the AD9042 has superior SFDR OMSPS AD9022/AD9023(20MSPS), AD9026/AD9027 31MSPS), and the AD9042(40 performance SEDR COMPARISON BETWEEN 12-BIT SAMPLING ADCs FOR (dBc) AD9042 D9026AD9027 INPUT FREQUENCY(MHz) Figure 5.12 The AD9042 is a state-of-the-art 12-bit, 40MSPS two stage subranging adc consisting of a 6-bit coarse ADC and a 7-bit residue adC with one bit of overlap to correct for any dNL, INL, gain or offset errors of the coarse ADC, and offset errors in the residue path. a block diagram is shown in Figure 5. 13. A proprietary gray. code architecture is used to implement the two internal ADCs. The gain alignment of the coarse and residue, likewise the subtraction Dac, rely on the statistical matching of the process. As a result, 12-bit integral and differential linearity is obtained without laser trim. The internal daC consists of 126 interdigitated current sources. Also on the dac reference are an additional 20 interdigitated current sources to set the coarse gain, residue gain, and full scale gain. The removes the requirement for laser trim. The AD9042 is fabricated on a high speed dielectrically isolated complementary bipolar process. The total power dissipation is only 575mW when operating on a single +5V supply1 2 requirement, you will generally require an ADC having a much higher sampling rate than is actually needed. Figure 5.12 shows the approximate SFDR versus input frequency for the AD9022/AD9023 (20MSPS), AD9026/AD9027 (31MSPS), and the AD9042 (40MSPS) series of low distortion ADCs. Notice that the AD9042 has superior SFDR performance. SFDR COMPARISON BETWEEN 12-BIT SAMPLING ADCs Figure 5.12 The AD9042 is a state-of-the-art 12-bit, 40MSPS two stage subranging ADC consisting of a 6-bit coarse ADC and a 7-bit residue ADC with one bit of overlap to correct for any DNL, INL, gain or offset errors of the coarse ADC, and offset errors in the residue path. A block diagram is shown in Figure 5.13. A proprietary gray￾code architecture is used to implement the two internal ADCs. The gain alignments of the coarse and residue, likewise the subtraction DAC, rely on the statistical matching of the process. As a result, 12-bit integral and differential linearity is obtained without laser trim. The internal DAC consists of 126 interdigitated current sources. Also on the DAC reference are an additional 20 interdigitated current sources to set the coarse gain, residue gain, and full scale gain. The interdigitization removes the requirement for laser trim. The AD9042 is fabricated on a high speed dielectrically isolated complementary bipolar process. The total power dissipation is only 575mW when operating on a single +5V supply