BLOCK DIAGRAM OF AD9042 12-BIT, 40MSPS ADC SHAZ ,〓(Σ DIGITAL ERROR CORRECTION AND OUTPUT REGISTERS Figure 5.13 AD9042 12-BIT 40MSPS ADC KEY SPECIFICATIONS Input Range: 1V peak-to-peak, Vom=+2.4V Input Impedance: 250Q2 to Vcm Effective Input Noise: 0.33 LSBs rms SFDR at 20MHz Input: 80dB S/(N+D)at 20MHz Input = 66dB Digital Outputs: T mpa e Power Supply: Single +5V Power Dissipation: 575mW Fabricated on High Speed Dielectrically Isolated Complementary Bipolar Process Figure 5.14 The outstanding performance of the AD9042 is partly due to the use of differential techniques throughout the device. The low distortion input amplifier converts the single-ended input signal into a differential one. If maximum SFDR performance is desired, the signal source should be coupled directly into the input of the AD9042 without using a buffer amplifier. Figure 5.15 shows a method using capacitive coupling.1 3 BLOCK DIAGRAM OF AD9042 12-BIT, 40MSPS ADC Figure 5.13 AD9042 12-BIT, 40MSPS ADC KEY SPECIFICATIONS Input Range: 1V peak-to-peak, Vcm = +2.4V Input Impedance: 250 to Vcm Effective Input Noise: 0.33LSBs rms SFDR at 20MHz Input: 80dB S/(N+D) at 20MHz Input = 66dB Digital Outputs: TTL Compatible Power Supply: Single +5V Power Dissipation: 575mW Fabricated on High Speed Dielectrically Isolated Complementary Bipolar Process Figure 5.14 The outstanding performance of the AD9042 is partly due to the use of differential techniques throughout the device. The low distortion input amplifier converts the single-ended input signal into a differential one. If maximum SFDR performance is desired, the signal source should be coupled directly into the input of the AD9042 without using a buffer amplifier. Figure 5.15 shows a method using capacitive coupling