Stimuli Inputs for Sequential Circuit Testing initial begin In order to reduce chance The timing is so #13 rst=1'b1; of several inputs chosen to cover at #19 d_in=4b1000; changing at the same least one positive time,we usually use clock edge #31 rst=0'b0; prime numbers for #330 $finish; timing of sequential end circuit inputs. always #37 d_in d_in 3; The initial block generates a d_in input is assigned a positive pulse on rst that begins always #11 clk =~clkj new value every 37 ns. at 13 ns and ends at 63 ns. Toggles every 11ns Name 406018011001 1201 1401160180200220249-260128013001320,3403601380 0 ps clk rst 0 din d out ASIC Design,by Yan Bo 25ASIC Design, by Yan Bo 25 Stimuli Inputs for Sequential Circuit Testing initial begin #13 rst=1'b1; #19 d_in=4'b1000; #31 rst=0'b0; #330 $finish; end always #37 d_in = d_in + 3; always #11 clk = ~clk; The timing is so chosen to cover at least one positive clock edge The initial block generates a positive pulse on rst that begins at 13 ns and ends at 63 ns. In order to reduce chance of several inputs changing at the same time, we usually use prime numbers for timing of sequential circuit inputs. Toggles every 11ns d_in input is assigned a new value every 37 ns