Testbench for SRAM with bidirectional data port module test RAM_static_BD;/Demonstrate write/read capability. 0 CS b Latched/Read mode reg bus_driver,CS_b,WE_b,OE_b; IWEb一 0OEb wire data_read=(WE_b ==1)?data_bus:1'bz; latch out wire data_bus =((WE_b ==0)&&(OE_b==1))?bus_driver:1'bz; RAM_static_BD M1(data_bus,CS_b,OE_b,WE_b); initial #4500 $finish; initial begin CS_b=1;OE_b=1;bus_driver=1; #500CSb=0; 透明模式WEb=0且OEb=1): #500WEb=0; bus_driverf传到data_bus,latch_out; #100 bus_driver=0;#100 bus_driver=1; 写模式WEb=0->1且OE_b=1): #300WE_b=1; 断开bus_driver,锁存并送到data_bus; #200 bus driver=0; 读模式(WEb=1且OEb=0): #3000E_b=0;#2000E_b=1;#2000E_b=0; latch_outi送至data_bus,data_read #300OE_b=1;WEb=0;#200WE_b=1; 其余情况：latch锁存，data为高阻值 #2000Eb=0;#2000E_b=1; #500CSb=1; test_RAM static BD #500 bus_driver=0; Transparent mode No driver Chip de-selected end 142N 240 42601 Nam data read initial begin WE WE b #3600WE_b=1;OE_b=1; OE WE RAM_static_BD data ■bus driver #200WE_b=0;OE_b=0; OE CS data_bus end CS b endmodule ■OE_b 2021/1/13 ASIC Design,by Yan Bo 24ASIC Design, by Yan Bo module test_RAM_static_BD; // Demonstrate write / read capability. reg bus_driver，CS_b, WE_b, OE_b; wire data_read = (WE_b == 1) ? data_bus : 1'bz; wire data_bus = ((WE_b == 0) && (OE_b == 1)) ? bus_driver : 1'bz; RAM_static_BD M1 (data_bus, CS_b, OE_b, WE_b); initial #4500 $finish; initial begin CS_b = 1; OE_b = 1; bus_driver = 1; #500 CS_b = 0; #500 WE_b = 0; #100 bus_driver = 0; #100 bus_driver = 1; #300 WE_b = 1; #200 bus_driver = 0; #300 OE_b = 0; #200 OE_b = 1;#200 OE_b = 0; #300 OE_b = 1; WE_b = 0; #200 WE_b = 1; #200 OE_b = 0; #200 OE_b = 1; #500 CS_b = 1; #500 bus_driver = 0; end initial begin #3600 WE_b = 1; OE_b = 1; #200 WE_b = 0; OE_b = 0; end endmodule Testbench for SRAM with bidirectional data port  透明模式(WE_b == 0 且 OE_b == 1)： bus_driver传到data_bus，latch_out；  写模式(WE_b == 0->1 且 OE_b == 1)： 断开bus_driver，锁存并送到data_bus；  读模式(WE_b == 1 且 OE_b == 0) ： latch_out送至data_bus, data_read  其余情况：latch锁存，data为高阻值 2021/1/13 24