Verilog for SRAM with bidirectional data port 0CSb■ 1 Latched/Read mode data bus 1WEb■ 0OEb■ bus driver CSb■dCS latch_out data RAM_static BD WEbWE data OEbOE module RAM static_BD(data,CS_b,OE_b,WE_b); inout data input CS_b,OE_b,WE_b; wire latch_out= ((CS_b ==0)&&(WE_b ==0)&&(OE_b ==1))?data:latch_out assign data ((CS_b ==0)&&(WE b==1)&&(OE b==0))?latch_out 1'bz endmodule 2021/1/13 ASIC Design,by Yan Bo 23ASIC Design, by Yan Bo Verilog for SRAM with bidirectional data port module RAM_static_BD (data, CS_b, OE_b, WE_b); inout data ; input CS_b, OE_b, WE_b; wire latch_out = ((CS_b == 0) && (WE_b == 0) && (OE_b == 1)) ? ; assign data = ((CS_b == 0) && (WE_b == 1) && (OE_b == 0)) ? ; endmodule 2021/1/13 23 latch_out : 1'bz data: latch_out