采用寄存器的推论方式表示RT级描述 library ieee; use ieee std _ logic_1164.all entity data_delay port(din in std logic; elkin std_logic; enable: in std _ logic; dout: out std_logic); end data delay architecture one of datadelay is signalql, q 2: std_logic, begin reg -p process egin waituntil clk’ event and clk=‘1 q1<=din; q2<=q1; end process reg-p; dout<=q1 when enable=1 else g2; end one采用寄存器的推论方式表示RTL级描述 library ieee; use ieee.std_logic_1164.all; entity data_delay is port(din:in std_logic; clk:in std_logic; enable:in std_logic; dout:out std_logic); end data_delay; architecture one of data_delay is signal q1, q2: std_logic; begin reg_p:process begin wait until clk’event and clk=‘1’; q1<=din; q2<=q1; end process reg_p; dout<=q1 when enable=‘1’ else q2; end one;