library ieee; use ieee std_logic_1164. all entity data delay is port(dinin std logic, clk:in std _ logic; enable in std _ logic; dout: out std logic) end data delay architecture one of data_delay is component dff port(d: in std_logic; clk: in std_logic; g: out std_logic); end component; signal g-_tmpl, g-_tmp2: std logic; begin dff1: dff port map(din,clk, g-_tmp1); dff2: dff port map(a_tmpl, clk, _tmp2); dout<=q_tmp1 when enable else 4-tmp2 end onelibrary ieee; use ieee.std_logic_1164.all; entity data_delay is port(din:in std_logic; clk:in std_logic; enable:in std_logic; dout:out std_logic); end data_delay; architecture one of data_delay is component dff port(d: in std_logic; clk: in std_logic; q: out std_logic); end component; signal q_tmp1, q_tmp2: std_logic; begin dff1: dff port map(din,clk, q_tmp1); dff2: dff port map(q_tmp1, clk, q_tmp2); dout<=q_tmp1 when enable=‘1’ else q_tmp2; end one;