Key Point of Combinational Design a Design with 2 input And gate is not as easy as 1+1=2 a We need to consider the Trace Delay and Gate Delay for Combinational Logic ■ Functional: The output of c is“0” a Timing: The output of c has a glitch with 3ns width a In this example the 3ns glitch is caused by trace Delay a Engineer Design Circuit work with Timing not Functional only Copyright 1997 Altera Corporation 9/12/97Copyright © 1997 Altera Corporation 9/12/97 Key Point of Combinational Design ◼ Design with 2 input AND gate is not as easy as 1+1=2 ◼ We need to consider the Trace Delay and Gate Delay for Combinational Logic ◼ Functional : The output of C is “0” ◼ Timing : The output of C has a Glitch with 3ns width ◼ In this example, the 3ns Glitch is caused by Trace Delay ◼ Engineer Design Circuit work with Timing not Functional only