Design of Combinational Circuit Danny Mok Altera HK FAE (amok@altera.com) bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Design of Combinational Circuit Danny Mok Altera HK FAE (dmok@altera.com)
What is combinational circuit Combinational circuit if Outputs at a specificed time are a function only of the INPUTS at that time example of combinational circuit address decoders ° multiplexers adders bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 What is Combinational Circuit ◼ Combinational Circuit if – Outputs at a specificed time are a function only of the INPUTS at that time – example of combinational circuit • address decoders • multiplexers • adders
Example There are three parts within this design LPM AVALUE LPM DIRECTIONEUP Which part is the Combinational Logic? MODULUS= LPMISVALUE - CLIQUE LPM IDTH=3 PM COUNTE 'PROBE1 Preset counter value Is 7 >out ABRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Example There are three parts within this design Which part is the Combinational Logic ? Preset when counter value is H”7
Simulation result What is the Expect Output U DFECT MF UF 顺UU D reset IPM COUNTER clk 「「「L「L「 clk2 q2.0 001001 000X X34X5670 X What do you get 100.0ns -reset 0 aqg叫010x1X2-345X670X1 Copyright 1997 Altera Corporation 9/12/97 Error
Copyright © 1997 Altera Corporation 9/12/97 Simulation Result What is the Expect Output What do you get Error
Altera Device has problem I can not use it anymore I never use it again No no no It is not altera How Device problem OK!I can prove it to you bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Altera Device has problem I can not use it anymore I never use it again No, no, no.... It is not Altera Device problem OK ! I can prove it to you How ?
The Simplest Combinational Circuit Nothing can be simplest than 2 input ANd Gate or 2 input OR Gate a 2 input and/oR gate is as simple as 1+1=2 DD Altera Device can not handle this so Simple circuit bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 The Simplest Combinational Circuit ◼ Nothing can be simplest than 2 input AND Gate or 2 input OR Gate ◼ 2 input AND/OR gate is as simple as 1+1 = 2 Altera Device can not handle this so Simple Circuit
2 input AND Gate But are you sure it is really so Simple????? 通D2 Y alue Iww.viV What happen? It must be Altera Device problem Input Waveform Name value IU,UlIs ∠,U C bBRA Copyright 1997 Altera Corporation Output Wa、orm 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 2 input AND Gate Input Waveform Output Waveform What happen ? It must be Altera Device Problem But are you sure it is really so Simple ?????
Take a closer look assume the and gate internal delay is 0.2ns Look at the delay matrix What is it means Delay matrix Simple Arithmetic Calculation For Signal b 11.1ns (Trace delay of b)+ ANd gate internal delay =8.Ins (Trace delay of b)+. 2ns=8.1 (Trace delay of b)=7.9ns For Signal a (Trace delay of a)+ AND gate internal delay =11. Ins (Trace delay of a)+0.2ns=11.1 (Trace delay of a)=10.9ns stop List Paths bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Take a closer look Look at the Delay Matrix What is it means ? Assume the AND gate internal delay is 0.2ns Simple Arithmetic Calculation For Signal b : (Trace delay of b) + AND gate internal delay = 8.1ns (Trace delay of b) + 0.2ns = 8.1ns (Trace delay of b) = 7.9ns For Signal a : (Trace delay of a) + AND gate internal delay = 11.1ns (Trace delay of a) + 0.2ns = 11.1ns (Trace delay of a) = 10.9ns
(Trace delay of a)=10.9ns (Trace delay of b)=7.9ns Time: 0 ibeas 0->1 Outpatftpchanghaagk from"a"to"D"ats&hlenfinal result aa Duae 10 Ref:1626ns Time: 1737ns Interval:11.1ns Name value. 1000ns 0 ALBRA Copyright 1997 Altera Col 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Time : 0ns 1->0 0->1 0 0 1 (Trace delay of b) = 7.9ns (Trace delay of a) = 10.9ns Time : 7.9ns 0 1 0 1 Time : 8.1ns 1 0 1 1 1 Time : 10.9ns 1 0 1 1 1 Time : 11.1ns 0 0 1 0 1 0 Output C change from “0” to “1” at 8.1ns A 3 ns Pulse generate (10.9-7.9 = 3ns) Output C change back from “1” to “0” as the final result
Key Point of Combinational Design a Design with 2 input And gate is not as easy as 1+1=2 a We need to consider the Trace Delay and Gate Delay for Combinational Logic ■ Functional: The output of c is“0” a Timing: The output of c has a glitch with 3ns width a In this example the 3ns glitch is caused by trace Delay a Engineer Design Circuit work with Timing not Functional only Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Key Point of Combinational Design ◼ Design with 2 input AND gate is not as easy as 1+1=2 ◼ We need to consider the Trace Delay and Gate Delay for Combinational Logic ◼ Functional : The output of C is “0” ◼ Timing : The output of C has a Glitch with 3ns width ◼ In this example, the 3ns Glitch is caused by Trace Delay ◼ Engineer Design Circuit work with Timing not Functional only
