Powerful of CLIQUE Danny Mok Altera HK FAE (amok@altera.com) Copyright 1997 Altera Corporation 2/22/2021P1 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.1 Powerful of CLIQUE Danny Mok Altera HK FAE (dmok@altera.com)
Architecture of fleX device FastTrack M Interconnect Same row LAB Copyright 1997 Altera Corporation 2/22/2021P2 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.2 Architecture of FLEX Device FastTrack™ Interconnect LAB Same ROW
Figure 8. LAB Connections to Row& Column Interconnect 16 Column Channels Row Channels Each le drives one LE1 ▲▲▲ LE2 Each LE drives up to Feedback Feedback two column channels Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.3
Three Routing Possibility Routing Timing analyze 回区 Registered Performance Clock: ource Fasttrack Interconnect Destination eriod: 4. Ons y250.00MHz Start Minimum delay LC->LC Copyright 1997 Altera Corporation 2/22/2021P4 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.4 Three Routing Possibility FastTrack™ Interconnect Minimum Delay LC -> LC Routing 1
Three Routing Possibility Routing 2 目|目|目 FastTrackTM Interconnect 口区 Registered Performance Clock. Destination Medium dela Clock period: 5.5ns Frequency: 181.81MHz LC->ROW->LC Copyright 1997 Altera Corporation Start stop List Paths 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.5 Three Routing Possibility FastTrack™ Interconnect Medium Delay LC -> ROW -> LC Routing 2
Three Routing Possibility 了口回mmAm □区 Routin g 3 Registered Performance Clock: ck (1 paths) FasttrackM Interconnect Source:: 1.0 Destination:: 2.0 150 日日 Clock period: 7.3ns Frequency: 1 2 Maximum delay Start Stop ist Paths LC-> ROW->COL - LC Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.6 Three Routing Possibility FastTrack™ Interconnect Maximum Delay LC -> ROW -> COL -> LC Routing 3
Which one faster WichwodoogrtlASHNBSST?? Copyright 1997 Altera Corporation 2/22/2021P7 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.7 Which one faster ? Which one run SLOWEST ? Which one run FASTEST ? How about this one ?
What is CLIQUE Clique is an option which provided by altera Max+ Plus l which used to control the logic placement force the logic placement within the same LAB(no ROW/CoLUMN trace delay)--Highest speed the same RoW(no CoLUMn trace delay) Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.8 What is CLIQUE ? ◼ Clique is an option which provided by Altera Max+Plus II which used to – control the logic placement – force the logic placement within • the same LAB (no ROW/COLUMN trace delay) -- Highest speed • the same ROW (no COLUMN trace delay)
Where is this Option Assign Options Help Device Pin/Location/Chip Timing Requirements Clique Chque Top of Hierarchy d: \503\new 32wxgq gdf Logic Options Node Name: 32wxgg:1 Probe OK Connected Pins Clique Na Cancel Local routing. Global Project Device Options Existing Clique Assignments Search [32wxgg: 1lsub1: 762 >sub-group1 Global Project Parameters 3 Sort By Global Project Timing Requirements C Node Name Global Project Logic Synthesis C Clique Name Ignore Project Assignments Clear Project Assignments Back- Annotate Projet Delete Convert Obsolete Assignment Format Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.9 Where is this Option ?
Example 三 三 三三三 二 三E…二 一-- No Hierarchy design, all is TtL No way to apply CLIQue 2/22/2021P10 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.10 Example No Hierarchy design, all is TTL, No way to apply CLIQUE
