《计算机英语》Asynchronous Circuit Design

Asynchronous vs Synchronous Circuit Design Danny Mok Altera HK FAE (amok@altera.com) bBRA Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Asynchronous vs Synchronous Circuit Design Danny Mok Altera HK FAE (dmok@altera.com)

Asynchronous Circuit Design a Mainly use Combinational Logic to do the decoding Address decoder Fifo/Ram Read or Write pulse a The output logic does not have any relationship with any clocking signal a Usually the Decoding Glitch can be monitored at the output signal Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Asynchronous Circuit Design ◼ Mainly use Combinational Logic to do the decoding – Address decoder – Fifo/Ram Read or Write pulse ◼ The output logic does not have any relationship with any clocking signal ◼ Usually the Decoding Glitch can be monitored at the output signal

Synchronous circuit Design a Usually the circuit design will involve with different kind of flip-Flop D type, JK type, Rs type or T type a The output logic is fully control by the rising edge or falling edge of the same clocking signal ■ No Glitch wil‖ be experienced at the output signal Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Synchronous Circuit Design ◼ Usually the circuit design will involve with different kind of Flip-Flop – D type, JK type, RS type or T type ◼ The output logic is fully control by the rising edge or falling edge of the same clocking signal ◼ No Glitch will be experienced at the output signal

Asynchronous Design Example u↑pu 7439go LCLKB LQD cla 1CLKA IQc OUTPUT O2N O3N 日 C OSN On On b BCDTO DEC Binary counter: LLLL LLLH bCd to dec. LllL-> HHHHHHHHHL LLHL LLLH-> HHHHHHHHLH LLHH LLHL→> HHHHHHHLHE LLHH->HHHHHHLHHH HHHE Copyright 1997 Altera Corporation HLLH->LHHHHHHHHH 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Asynchronous Design Example Binary Counter : LLLL LLLH LLHL LLHH .......... HHHH BCD to DEC : LLLL -> HHHHHHHHHL LLLH -> HHHHHHHHLH LLHL -> HHHHHHHLHH LLHH -> HHHHHHLHHH .......... -> ............................ HLLH -> LHHHHHHHHH

Expect Output Start: 0.Ons ]□」End「1us Interval: 1. Ous ‖Name Value 100 Ons 200.ns 300 Ons 400 Ons 500. Ons 0000 This is the dLE output waveform but what will we get really? bBRA Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Expect Output This is the IDLE output waveform but what will we get really ?

Functional Simulation Output Name value ∠UU| ++UU,UlIs cIra lka d2 0000 -o d1 What is this bBRA Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Functional Simulation Output What is this ?

Timing Simulation Output Nam value 100ns 200.ns 300.Ons 400.ns cIra lK l「「「「「 d3 o dO It get worst What is going on? Engineer Design problem or Altera Device Problem But .... It works with 74xX TtL logic and fail with altera device. it must be altera device problem bBRA Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Timing Simulation Output It get worst !!! What is going on ? Engineer Design problem or Altera Device Problem ? But ..... It works with 74xx TTL logic and fail with Altera Device, it must be Altera Device Problem

What is Happening Let us take a closer look of th/74390 and 7442 bBRA Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 What is Happening ◼ Let us take a closer look of the 74390 and 7442

7442 NANDA In order to have Glitch Free Q19.0N Output pi SULFur 1.)IF the output of 74390 reach the NAND4 at OGN the same time NANDA 2. )IF Trace Delay a equal to Trace Delay B p: SUTPUD oiN and equal to trace delay c NANDA and equal to Trace delay D UTPUT O2N NANDA 0are□ OCN N的NDa Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 7442 A B C D In order to have Glitch Free Q[9..0]N Output : 1.) IF the output of 74390 reach the NAND4 at the same time 2.) IF Trace Delay A equal to Trace Delay B and equal to Trace Delay C and equal to Trace Delay D

Does the f is reasonable Delay matrix Destination d3 m74421600UT0QNC 2. Ons m74421600UT1Q~NC 2. Ons Im7442. 1600UT20"NC m7442160UT3Q^NC 2. Ons 2. )IF Trace Delay a equal to Trace Delay E and equal to trace delay c and equal to Trace Delay d This condition is OK from The Delay Matrix ATIER/A Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Does the IF is reasonable ? 2.) IF Trace Delay A equal to Trace Delay B and equal to Trace Delay C and equal to Trace Delay D This condition is OK from The Delay Matrix