How to implement the circuit in EAB within VHDL coding Danny Mok Altera HK FAE (amok@altera.com) Copyright 1997 Altera Corporation 2/22/2021P1 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.1 How to implement the circuit in EAB within VHDL coding Danny Mok Altera HK FAE (dmok@altera.com)
State Machine Design .Design a state machine that will detect a Serial pattern of 011011 from a serial in stream .When this pattern is detected set match=output for one cycle Test your design by Input the following pattern“011101”,“011011” Serial in VHDL State Match Machine clk Copyright 1997 Altera Corporation 2/22/2021P2 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.2 State Machine Design •Design a state machine that will detect a Serial pattern of “011011” from a serial_in stream •When this pattern is detected set match = ‘1’ output for one cycle •Test your design by Input the following pattern “011101”, “011011” Serial_in Match clk VHDL State Machine
Sample VHDL coding library ieee if (clIk'event and clk='1)then when state01101 = if(seral in ='1)then use ieee std logic 1164 all case present state present state if(serial in =0)then present state if(serial in='1)then end if, library ieee present state < state01 end if, end process, use ieee std logic 1164. al process(present state) use work. your own type. all present state < idle Entity sth is end if if (present state =state011011)then port (clk, serial in, reset: in std logic when state0l = if (serial in=,)then match c'l present state < stateOll match: out std logic) match <=0 end sth nd if, present state <= idle end process; architecture body_ sth of stmh is end if end body sth signal present state: t state, when state0ll = if(serial in =0)then egin present state < state0110 process(clk, serial in, present state) ent state < idle end if if (reset ='1)then when state0110 = if(serial in ='1")then present state <=idle present state<= state01101 pyright 1997 Altera Corporation present state < idle 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.3 Sample VHDL coding library ieee; use ieee.std_logic_1164.all; package your_own_type is type t_state is (idle,state0,state01,state011, state0110,state01101, state011011); end your_own_type; library ieee; use ieee.std_logic_1164.all; use work.your_own_type.all; Entity stmh is port (clk, serial_in, reset : in std_logic; match : out std_logic); end stmh; architecture body_stmh of stmh is signal present_state : t_state; begin process(clk,serial_in, present_state) begin if (reset = '1') then present_state if (serial_in = '1') then present_state present_state present_state if (serial_in = '0') then present_state if (serial_in = '1') then present_state if (serial_in = '1') then present_state if (serial_in = '0') then present_state if (serial_in = '1') then present_state <= state01101; else present_state <= idle; end if;
How do l implement this within EAB library ieee if (clIk'event and clk='1)then when state01101 = if(seral in ='1)then use ieee std logic 1164 all case present state is present state if(serial_in=)then present state <=idle present _s te <=stateol pyright 1997 Altera Corporation present state < idle 2/22/2021P4 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.4 How do I implement this within EAB library ieee; use ieee.std_logic_1164.all; package your_own_type is type t_state is (idle,state0,state01,state011, state0110,state01101, state011011); end your_own_type; library ieee; use ieee.std_logic_1164.all; use work.your_own_type.all; Entity stmh is port (clk, serial_in, reset : in std_logic; match : out std_logic); end stmh; architecture body_stmh of stmh is signal present_state : t_state; begin process(clk,serial_in, present_state) begin if (reset = '1') then present_state if (serial_in = '1') then present_state present_state present_state if (serial_in = '0') then present_state if (serial_in = '1') then present_state if (serial_in = '1') then present_state if (serial_in = '0') then present_state if (serial_in = '1') then present_state <= state01101; else present_state <= idle; end if;
Let us view the Design in Graphic Feedback pa State Machine Register Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.5 Let us view the Design in Graphic State Machine Register Feedback path
Study the State Machine Design a How many State of this State Machine Idle State0. State01. State011. State0110. state01101 State011011 7 states, can use 3 bits to implement it a How many output from this design Match, State Machine(3 bits) 4 bit to implement it a How many Input signal for this design Serial in, State Machine (3 bits) 4 bits can implement it a Where is the Clock signal use for Use for the dff of the state machine Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.6 Study the State Machine Design ◼ How many State of this State Machine – Idle, State0, State01, State011, State0110, State01101, State011011 • 7 states, can use 3 bits to implement it ◼ How many output from this design – Match, State_Machine (3 bits) • 4 bit to implement it ◼ How many Input signal for this design – Serial_in, State_Machine (3 bits) • 4 bits can implement it ◼ Where is the Clock signal use for – Use for the DFF of the State Machine
■ Feedback path Use to feedback the output to the input of the state machine case present state IS when idle =>if (serial in=0)then present state <=state0 else present state dle en Copyright 1997 Altera Corporation 2/22/2021P7 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.7 ◼ Feedback Path – Use to feedback the output to the input of the state machine case present_state is when idle => if (serial_in = '0') then present_state <= state0; else present_state <= idle; end if;
Does Altera 10K EAB support the requirement a Total Input -4 input (OK) Total Output-4 output(OK) Total Bit requirement to implement the State Machine 2*4*4=64 bits < 2Kbits(OK) a Input Register -Not used (OK) a Output Register-All used (OK) a Does not support RESET(Remove) ■ Feedback path? Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.8 Does Altera 10K EAB support the requirement ◼ Total Input - 4 input (OK) ◼ Total Output - 4 output (OK) ◼ Total Bit requirement to implement the State Machine – 2**4 * 4 = 64 bits <= 2Kbits (OK) ◼ Input Register - Not used (OK) ◼ Output Register - All used (OK) ◼ Does not support “RESET” (Remove) ◼ Feedback Path ?
Review of eab of 1ok device DATA 8,42,1 RAM/ROM wide 8,4.2 256X8 wide ADDR 512×4 1.10.9 wide ° Does mlot WE oh Suport Feec bask path Input Pulse CLK Circuit Output CLK Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.9 Review of EAB of 10K Device D RAM/ROM 256x8 512x4 1024x2 2048x1 D D D Write Pulse Circuit Q: 8,4,2,1 wide DATA: 8,4,2,1 wide ADDR: 11,10,9,8 wide WE Input CLK Output CLK
Is it correct ibrary ieee if(clk' event and clk='1)then when state0110=> if (serial in='1)then use ieee std logic 1164. all case present state when idle = if(serial in =0) next state if(serial in='1 )then library ieee when state serial in next state next state if( seral_ in=0)then present_state <=next_state, begin next state < state0110. next state < idle Copyright 1997 Altera Corporation match <=0 end if, 2/22/2021P10 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.10 Is it correct ? when state0110 => if (serial_in = '1') then next_state if (serial_in = '1') then next_state next_state next_state if (serial_in = '0') then next_state if (serial_in = '1') then next_state if (serial_in = '1') then next_state if (serial_in = '0') then next_state <= state0110; match <= '0'; else next_state <= idle; match <= '0'; end if;