《计算机英语》Beginner VHDL Training Class

Beginner VHDl Training Class Danny Mok Altera HK FAE (amok@altera.com) Copyright 1997 Altera Corporation 2/22/2021P1 favara

Copyright © 1997 Altera Corporation 2/22/2021 P.1 Beginner VHDL Training Class Danny Mok Altera HK FAE (dmok@altera.com)

What is vhdl a Very high speed integrated Hardware Description Language(VHDL) is an industry standard hardware description language description the hardware in language instead of graphic easy to modify ° easy to maintain very good for complex combinational logic BCD to 7 Segment converter address decoding state machine · more than you want... Copyright 1997 Altera Corporation 2/22/2021P2 favara

Copyright © 1997 Altera Corporation 2/22/2021 P.2 What is VHDL ◼ Very high speed integrated Hardware Description Language (VHDL) – is an industry standard hardware description language – description the hardware in language instead of graphic • easy to modify • easy to maintain – very good for • complex combinational logic – BCD to 7 Segment converter – address decoding • state machine • more than you want……

What vhdl standard means?? The Vhdl is used to describe Inputs port Outputs port behavior and functions of the circuits unctions Output port Inputs port …e UTPUT out The language is defined by two successive standards IEEE Std 1076-1987(called VHDL 1987) IEEE Std 1076-1993(called VHDL 1993) Copyright 1997 Altera Corporation 2/22/2021P favara

Copyright © 1997 Altera Corporation 2/22/2021 P.3 What VHDL Standard means?? ◼ The VHDL is used to describe – Inputs port – Outputs port – behavior and functions of the circuits ◼ The language is defined by two successive standards – IEEE Std 1076-1987 (called VHDL 1987) – IEEE Std 1076-1993 (called VHDL 1993) Inputs port Output port functions

Altera Vhdl Altera Max+ Plus support both VHDL 1987 and 1993 a Max+ Plus l only support SUBSET of the two IEEE standard a Detail of the support can be referred to Altera Max+Plus VHDL handbook on page 89 Section 3 Copyright 1997 Altera Corporation 2/22/2021P4 favara

Copyright © 1997 Altera Corporation 2/22/2021 P.4 Altera VHDL ◼ Altera Max+Plus II support both VHDL 1987 and 1993 ◼ Max+Plus II only support SUBSET of the two IEEE standard ◼ Detail of the support can be referred to Altera Max+Plus II VHDL handbook on page 89 Section 3

How to use the vhdl use any text editor to create the file Altera Software Max+ Plus li provides text editor 喻净MAX+ plus Il Manager+dmax2work MAX+plus II File Assign Options Help 回回回圖圖回图圆國郾感网圈网画圆 New click at File Type this icon C Graphic Editor file gdf C Symbol Editor file tExt Editor file C Waveform Editor file scf OK Cancel Copyright 1997 Altera Corporation 2/22/2021P favara

Copyright © 1997 Altera Corporation 2/22/2021 P.5 How to use the VHDL ◼ use any text editor to create the file – Altera Software Max+Plus II provides text editor click at this icon

■ create your VHDL file Fe Untitled2- Text Editor entity test is port ( a: in std logic; b:out std logic); architecutre a of test is begin b < not a. end a? Copyright 1997 Altera Corporation 2/22/2021P favara

Copyright © 1997 Altera Corporation 2/22/2021 P.6 ◼ create your VHDL file

u save your Vhdl file as name. VHD Qo MAX+plus -d: \ max2work \a MAN+plus Eile Edit Iemplates Assign Utilities The name must be the same entity test port (a: in std logic; b: out std logic) architecutre a of test is begin b<= not a: Save As Directory is: d: \ max2work segment. tdf or advan. tdf ax2work decoder tdf flip flop tdf Drives. Ipm mult1. tdf Automatic Extension tdf Copyright 1997 Altera Corporation OK 2/22/2021P7 favara

Copyright © 1997 Altera Corporation 2/22/2021 P.7 ◼ save your VHDL file as name.VHD The name must be the same

Select the Standard Version of VHDL coding 1987or1993 o MAX+plus II-c: \max2work \vhdL \ adder HDL Netlist Reader Settings AX+plus ll File Processing Interfaces Assign Options Window ! VHDL Version 囗圖圖国国 EDIF Netlist Reader Settings C VHDL 1987 C VHDL 1993 EDIF Netlist writer EDIF Netlist Writer Settings Project Libraries Verilog Netlist Writer Compiler Verilog Netlist Writer Settings Directory Name Compiler VHD) Netist Reader Seting. i: mam2work Directorie Netlist /HDL Netlist writer Select which Extractor VHDL Netlist writer Settings version you XNF Netlist Reader Settings want Existing Synopsys Compiler Syrippsys Compiler Settings Start Cancel Copyright 1997 Altera Corporation 2/22/2021P favara

Copyright © 1997 Altera Corporation 2/22/2021 P.8 ◼ Select the Standard Version of VHDL coding – 1987 or 1993 Select which version you want

■ Compile your VHDL file MA+plus ll File Processing Interfaces Assign Options window Help 回圖 囚國國鬯國圖啁闔圖 Partitioner start 女Me Warning: Timing characteristics of device EPF MAX+plus ll -Compiler Project compilation was successful 4 Message o of 1 K Help on Message k Locate>0 of 0 i ocate Ail Copyright 1997 Altera Corporation DONE 2/22/2021P

Copyright © 1997 Altera Corporation 2/22/2021 P.9 ◼ Compile your VHDL file DONE !

Bonus Topic may help for VHDL Design within Max+PIus‖ Copyright 1997 Altera Corporation 2/22/2021P10 favara

Copyright © 1997 Altera Corporation 2/22/2021 P.10 Bonus Topic may help for VHDL Design within Max+Plus II