Setup/Hold Time Problem Danny Mok Altera HK FAE (amok@altera.com) bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Setup/Hold Time Problem Danny Mok Altera HK FAE (dmok@altera.com)
Example 1 DF d吕 OUTPU↑ q1 Name Value 6.4ns 128ns d1 clk1 Is the design simple enough to course any error? Any Setup/Hold time problem? Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Example 1 Is the design simple enough to course any error ? Any Setup/Hold time problem?
Let us take a look L Simulator: Timing simulation 区 Simulation *i Messages. Simulator murato warning: Found hold time violation at 14. Ons on register: 1. 0 Start Timewarning: Found setup time violation at 18. 6ns on register 1.Q 厂 Use de v Setup/H Sta Rememb! Message 0 of 2 Locate in floorplan Editor Help on Message check op Locate >0 of0 L往(e What? I get Setup/ Hold time problem? Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Let us take a look Remember to turn on this Setup/Hold time check option What ? I get Setup/Hold time problem ?
oK What can i do Look at the Setup/Hold time Matrix from the Timing Analysis □区 Setup/Hold Time Analysis Setup time=2.2ns Clocks Hold time =0.7ns clk1 2.2ns/0.7ns nput Start Stop List Paths Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 OK, What can I do ? Look at the Setup/Hold time Matrix from the Timing Analysis Setup time = 2.2ns Hold time = 0.7ns
My Waveform Input Name 6.4ns 12.8ns Setup time= 2ns Hold time =0.Ins According to Setup/Hold Matrix How to fix Setup time needs=2.2ns It is easy. Extend the Setup time from 2ns to 2.2ns Hold time needs=0.7ns Extend the hold time from 0.Ins to 0.7ns bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 My Waveform Input Setup time = 2ns Hold time = 0.1ns According to Setup/Hold Matrix Setup time needs = 2.2ns Hold time needs = 0.7ns How to fix ? It is easy. Extend the Setup time from 2ns to 2.2ns Extend the Hold time from 0.1ns to 0.7ns
Correct Waveform Name: Value 6.4ns 12.8ns 19.二 d1 clk 1 Extend the Setup/hold time to remove the error We fix the simulation error. But do we really fix the error yet? Simulation: means all the INPUT WAVEFORM is designer provided. We can easily adjust the INPut WAVEFORM to remove the simulation error. We need to confirm that the rEal INPUT Waveform fullfil the Setup/Hold time requirement. If not we need to CONTROL THE LOGIC PLACEMENT to fullfil the real time signal bBRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Correct Waveform Extend the Setup/Hold time to remove the error We fix the simulation error. But do we really fix the error yet ? Simulation : means all the INPUT WAVEFORM is designer provided. We can easily adjust the INPUT WAVEFORM to remove the simulation error. We need to confirm that the REAL INPUT WAVEFORM fullfil the Setup/Hold time requirement. If not we need to CONTROL THE LOGIC PLACEMENT to fullfil the real time signal
Example 2 q1 All the Setup/Hold prblem between this tor: Timing simulatior 口 two FF Simulation Input: t5. scf Messages SImulator Simulation Time: 5000ns Start Time: 0.Ons End Time: 5000ns Warning: Found hold time violation at 12. ns on register :1.Q Use device Warning: Found hold time violation at 12. 2ns on register :1. Q 厂 Oscillation.0ns v Setup/Hold Warning: Found hold time violation at 12. 5ns on register:1.Q 厂 Check0 outputs 厂 Glitch o.0ns Warning: Found hold time violation at 15.8ns on register 1 Q Warning: Found setup time violation at 20.5ns on register 6Q Warning Found setup time violation at 23. 7 ns on register 6.0 匚 Start Pause Stop Open SCF ABRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Example 2 All the Setup/Hold prblem between this two FF
How to fix the problem Let us run the Register Performance Timing Analysis 2a Timing Analyzer 口区 Registe2t5.scf-waveform Editor Clock: clk1 (1 path: Ref: 1.6ns 6 Time: 4.8ns Interval: 3.2ns 15 Name Value Dd1 D clk1 Clock period: 6. 8ns Frequency: 147.05MHz The Input Clock Frequency only 3. 2ns width 300MHZ Start Stop List Paths ABRA Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 How to fix the problem Let us run the Register Performance Timing Analysis The Input Clock Frequency is only 3.2ns width ~300MHz
Conclusion a If the Setup/Hold time error happen on the Input Register(Example 1) run the Setup/Hold time Matrix to get information adjust the Input Waveform but double confirm with the rea time operation signal If the Setup/Hold time error happen between Two Register(Example 2) run the Register Performance to get Fmax make sure that the input clock frequency is less than or equal to the fmax Copyright 1997 Altera Corporation 9/12/97
Copyright © 1997 Altera Corporation 9/12/97 Conclusion ◼ If the Setup/Hold time error happen on the Input Register (Example 1) – run the Setup/Hold time Matrix to get information – adjust the Input Waveform but double confirm with the real time operation signal ◼ If the Setup/Hold time error happen between Two Register (Example 2) – run the Register Performance to get Fmax – make sure that the input clock frequency is less than or equal to the Fmax