《计算机英语》Mix Design Entry within Max+Plus ll

Mix Design Entry within Max+Plus ll Danny Mok Altera HK FAE (amok@altera.com) bBRA Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Mix Design Entry within Max+Plus II Danny Mok Altera HK FAE (dmok@altera.com)

Design Files support by Max+Plus l ■ Design File Entry Graphic Design File(*.GDF) Text Design Files(*. TDF) VHDL Design Files(*.VHD) -EDIF Input Files(.EDF) OrCad Schematic Files * SCH) Waveform Design Files( *. WDF) You are allow to mix this design file with each other Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 ◼ Design File Entry – Graphic Design File (*.GDF) – Text Design Files (*.TDF) – VHDL Design Files (*.VHD) – EDIF Input Files (*.EDF) – OrCad Schematic Files (*.SCH) – Waveform Design Files (*.WDF) ◼ You are allow to mix this design file with each other Design Files support by Max+Plus II

Graphic Design File Example ■ In this example, you wil‖ learn how to use the Graphic entry how to integrate the Vhdl design file in Graphic design how to integrate the AhDl design file in Graphic design how to integrate the ediF design file in Graphic design Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Graphic Design File Example ◼ In this example, you will learn – how to use the Graphic entry – how to integrate the VHDL design file in Graphic design – how to integrate the AHDL design file in Graphic design – how to integrate the EDIF design file in Graphic design

How to Create VHDL circuit symbol vhdl yhd Text editor 口区 ho MAX+plus ll-Untitled1 ENTITY vhdl Is MAX+plus ll Eile Edit Iemplates Assign Utilities PORT( a,b: in bit in std logic. Compiler END Uhd Compiler Database Logic ARCHITEC Netlist Builder Synthe Ctrl+F4 Ctrl+S BEGIN Extractor about Ctrl+ clout end vhdl Line 10 de file Ctrl+P Start Enter you VhDl coae Alt+F4 bBRA Copyright 1997 Altera Corporation Create a Symbol for Graphical use 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 How to Create VHDL circuit symbol Enter you VHDL code Create a Symbol for Graphical use

Use the VHDL symbol within Graphic Design Enter Symbol a MAX+plus II-d: \max2work\vhdI1-[Untitled -Gral t MAX+plus l Eile Edit view Symbol Assign Utilities Symbol Libraries 口园圖圖圖圖回圆國威 d: \max 2work c: \dan_lib c:\maxplus2\max2lib\prim Use this symbol just as you use 7400 c:\maxplus2\max2lib\mf c: \maxplus2 \max 2 b \mega lpm VHDL 1 Directory is: d: \max2work ABOUT ymbol Files Directories vhdl 国d Cancel bout: out bit: dbody OF vhdl Is Copyright 1997 Altera Corporation edout <a c or d: 9/12/97 Line 10 Col 17 i

Copyright © 1997 Altera Corporation 9/12/97 Use the VHDL symbol within Graphic Design Use this symbol just as you use 7400

How to create ahdl circuit symbol ahdl. tdf- Text editor ho MAX+plus ll-Untitled1 SUBDESIGN ahdl MAX+plus ll Eile Edit Iemplates Assign Utilities c a, b, c, d: input about,F compiler Ctrl+0 Compiler Database Logic about = a t Netlist Builder Synthe Ctrl+F4 clout = c Ctrl+S Extractor end Ctrl+ de file Input your Al Ctrl+P Start Alt+F4 Copyright 1997 Altera Corporation Create a Symbol for Graphical use 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 How to Create AHDL circuit symbol Input your AHDL code Create a Symbol for Graphical use

Use the AHDL symbol wihtin Graphic Design Enter Symbol 國 Untitled5:6 aphic]Editor Symbol Name: ahn Symbol Libraries VHDL c: \dan lib c: \megacore \lib c: \maxplus2\max lib \prim B ABOUT c:\maxplus 2\max 2lib\mf C CDOUT Directory is: d: \max2work Symbol Files hdll ahd 1 ABOUT C CDOUT Drives 回d Cancel Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Use the AHDL symbol wihtin Graphic Design

How to create EdiF circuit symbol 口区 (edif (rename EDIFledif1") ho MAX+plus ll-Untitled1 (edifVersion 2 00) MAX+plus ll Eile Edit Iemplates Assign Utilities (edifLevel g) (keywordMap (keywordLevel 0)) status E Compiler Ctrl+0 (tinest (author Compiler Database Logic Netlist Builder Synthe Ctrl+F4 Ctrl+S Extractor (library(r Ctrl+ (edifLeve (technolo (cell AND de file Ctrl+P Start Alt+F4 Line 1 Col 1+ ABRA Copyright 1997 Altera Corporation Create a Symbol for Graphical use 9/12/97 Read in the edif file to max+Plus il

Copyright © 1997 Altera Corporation 9/12/97 How to Create EDIF circuit symbol Read in the EDIF file to Max+Plus II Create a Symbol for Graphical use

Use the EDIF symbol wihtin Graphic Design Enter Symbol Symbol Name: edif Symbol Libraries VHDL 1 c: dan ib c: megacore\ ABOUT c: \maxplus 2 \max 2 lib\p COUT c: \maxplus 2\max2lib\mf c: \maxplus 2\max 2lib\mega lpm Directory is: d: \max2work Symbol Files Directories edi 1 户d丶 ahdl 1 CDOUT C CouT Drives 回d OK bBRA Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Use the EDIF symbol wihtin Graphic Design

Graphics Entry support a Graphics Entry can support VHDL AHDL EDIF ■Step 1 )Read in your VHDL/AHDL/EDiF design file 2 )File-> Create Default Symbol to create the symbol for graphIc use 3 )Open the Graphic editor 4. )use the Generate Symbol as you use 74xx series Copyright 1997 Altera Corporation 9/12/97

Copyright © 1997 Altera Corporation 9/12/97 Graphics Entry support..... ◼ Graphics Entry can support – VHDL, AHDL, EDIF ....... ◼ Step – 1.) Read in your VHDL/AHDL/EDIF design file – 2.) File -> Create Default Symbol to create the symbol for graphic use – 3.) Open the Graphic editor – 4.) use the Generate Symbol as you use 74xx series