Usage of FloorPlanner Danny Mok Altera HK FAE (amok@altera.com) Copyright 1997 Altera Corporation 2/22/2021P1 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.1 Usage of FloorPlanner Danny Mok Altera HK FAE (dmok@altera.com)
What is the Floorplan a It is use to control the placement of your design logic to increase the performance of your design to reduce the rowicolumn traffic resolve the "can not fit issue(Altera Expert can do this for ou use to control the trace delay a Logic Plan can not help you to simplify your design from a Complex to a Simple one Copyright 1997 Altera Corporation 2/22/2021P2 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.2 What is the Floorplan ◼ It is use to control the placement of your design logic – to increase the performance of your design – to reduce the ROW/COLUMN traffic – resolve the “can not fit” issue (Altera Expert can do this for you) – use to control the trace delay ◼ Logic Plan can not help you to simplify your design from a Complex to a Simple one
Why the Floorplan is so important The delay is a combinational of Two Factors Gate delay Trace Delay Two situation to consider Gate Delay >>> Trace Delay(floorplan is useless, logic complexity is more important Gate Delay <<< Trace Delay(floorplan is very important) a For Altera Device, Trace Delay is bigger than Gate Delay, so floorplan is important Trace dela Gate Delay at Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.3 Why the Floorplan is so important ◼ The Delay is a combinational of Two Factors – Gate Delay – Trace Delay ◼ Two situation to consider – Gate Delay >>>> Trace Delay (floorplan is useless, logic complexity is more important) – Gate Delay <<<< Trace Delay (floorplan is very important) ◼ For Altera Device, Trace Delay is bigger than Gate Delay, so floorplan is important Trace Delay Gate Delay
Example 1 at &a ti □回区 Delay Matrix Destinati cell-1-out Icell-2-out 2. 4ns Copyright 1997 Altera Corporation Start List Paths 2/22/2021P4 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.4 Example 1
Example 2 11.7-2. 4=9. 3ns delay caused by TRACE delay Timing Analyzer 口区 Delay matrix Destination Icell-l-out Icell-2-out 7. 2ns 18.ns Icell-1 rIcell-2-out Start Stop List Path Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.5 Example 2 11.7 - 2.4 = 9.3ns delay caused by TRACE DELAY
What Altera Floorplan can do Altera Floorplan can provide the designer to contro the O pin location the logic cell location a For the l/O pin, you can control the location at different row different Column a For the Logic Cell, you can control the location at different cell within LAB different LAB different Row different column Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.6 What Altera Floorplan can do ◼ Altera Floorplan can provide the designer to control – the I/O pin location – the logic cell location ◼ For the I/O pin, you can control the location at – different Row – different Column ◼ For the Logic Cell, you can control the location at – different cell within LAB – different LAB – different Row – different Column
cont a Before use the Floorplan to control the placment, you must back-annotate the project first you have the choice to lock down the Pin and logic cell lock down the Logic Cell Copyright 1997 Altera Corporation 2/22/2021P7 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.7 cont... ◼ Before use the Floorplan to control the placment, you must back-annotate the project first – you have the choice to • lock down the Pin and Logic Cell • lock down the Logic Cell
Back-Annotate the Project is the First Step (a MAX+plus II Manager-c: \max2 -working\delay Click on this button MA以+ plus ll EileAssign业 tilities Options window Help Back-Annotate project 口园回圈 Device Pin/Location/Chip Project Name is Timing Requ c: \max2-working \delay. gdf Clique Back-Annotate to ACF Logic Options v Chips, Logic Cells, Pins &Devices Probe Connected Pins 厂 Chips. Pins t devices Local Routing Chips Global Project Device Options 厂 Devices Global Project Parameters Global Project Timing Requirements OK Cancel Global Project Logic Synthesis Ignore Project Assignments 日日日 Demote Clear Project Assignments Back- Annotate Project 口口口 Convert Obsolete Assignment Format Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.8 Back-Annotate the Project is the First Step Click on this button
lo Location control- method 1 NICurrent Assignments)-Floorplan Editor 白白白当白白白白白白白白白 Change the Last Comp to Current 口口 K<none@LC1_Al Compilatio 日自「日 □ 日日日日旧 Copyright 1997 Altera Corporation ABRA 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.9 I/O Location Control - Method 1 Change the Last Compilation to Current Compilation
Drag and Place of the Device茴尚向向向向 Any where within this row 口口口 DATA 口‖口 日日|日 Copyright 1997 Altera Corporation Anywhere ithin 2/22/2021P10 At this particular 1/O pin this column favara
Copyright © 1997 Altera Corporation 2/22/2021 P.10 Drag and Place Anywhere of the Device Any where within this row Anywhere within this column At this particular I/O pin